89H16NT16G2ZBHLG IDT, 89H16NT16G2ZBHLG Datasheet - Page 4

• Manufacturer Part Number: 89H16NT16G2ZBHLG
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: IDT

Specifications of 89H16NT16G2ZBHLG

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes
• Part # Aliases: IDT89H16NT16G2ZBHLG

SSMBADDR2 pins. As shown in Figure 2, the master and slave SMBuses may only be used in a split configuration. In the split configuration, the
master and slave SMBuses operate as two independent buses; thus, multi-master arbitration is not required. The SMBus master interface does not
support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the SMBus lines that connect to the serial EEPROM
and I/O expander slaves.
Hot-Plug Interface
PES16NT16G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES16NT16G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES16NT16G2. In response to an I/O expander interrupt, the PES16NT16G2 generates
an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
outputs, or alternate functions. All GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus
slave interface, or serial configuration EEPROM.
Pin Description
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and
The PES16NT16G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
The PES16NT16G2 provides 9 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
The following tables list the functions of the pins provided on the PES16NT16G2. Some of the functions listed may be multiplexed onto the same
Note: Pin [x] of a port refers to a lane. For port 0, PE00RN[0] refers to lane 0, PE00RN[1] refers to lane 1, etc.
Switch
Figure 2 Split SMBus Interface Configuration
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
4 of 33
EEPROM
Processor
SMBus
Serial
Master
...
Expander
Hot-Plug
I/O
Devices
SMBus
Other
April 16, 2013