XRT83L38ES Exar, XRT83L38ES Datasheet - Page 71

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.2
D6
D5
D4
D3
D2
D1
D0
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MCLKRATE Master clock Rate Select: The state of this bit programs the
CLKSEL2
CLKSEL1
CLKSEL0
RXMUTE
EXLOS
T
ICT
ABLE
36: M
Clock Select Inputs for Master Clock Synthesizer bit 2:
In Host mode, CLKSEL[2:0] are input signals to a programma-
ble frequency synthesizer that can be used to generate a mas-
ter clock from an external accurate clock source according to
the following table;
In Hardware mode, the state of these signals are ignored and
the master frequency PLL is controlled by the corresponding
Hardware pins.
Clock Select inputs for Master Clock Synthesizer bit 1:
Clock Select inputs for Master Clock Synthesizer bit 0:
Master Clock Synthesizer to generate the T1/J1 or E1 clock.
The Master Clock Synthesizer will generate the E1 clock when
MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =
“1”.
Receive Output Mute: Writing a “1” to this bit, mutes receive
outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for
any channel that detects an RLOS condition.
N
Extended LOS: Writing a “1” to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
In-Circuit-Testing: Writing a “1” to this bit configures all the
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
See description of bit D6 for function of this bit.
See description of bit D6 for function of this bit.
M CLKE1
OTE
2048
2048
2048
1544
1544
2048
kHz
128
128
256
256
16
16
56
56
64
64
ICROPROCESSOR
8
8
: RCLK is not muted.
M CLKT1
2048
2048
1544
1544
1544
1544
kHz
X
X
X
X
X
X
X
X
X
X
X
X
CLKSEL2
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R
68
EGISTER
CLKSEL1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
#129, B
CLKSEL0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IT
M C LK RATE
D
ESCRIPTION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKO UT/
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
2048
1544
kHz
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XRT83L38
0
0
0
0
0
0
0