XRT83L38ES Exar, XRT83L38ES Datasheet - Page 25

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.2
FUNCTIONAL DESCRIPTION
The XRT83L38 is a fully integrated long-haul and short-haul transceiver intended for T1, J1 or E1 systems.
Simplified block diagrams of the chip are shown in
XRT83L38 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable loss)
for T1 and from 0 to 43dB at 1024kHz for E1 systems.
In T1 applications, the XRT83L38 can generate five transmit pulse shapes to meet the short-haul Digital Cross-
connect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB
and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators for
each channel that can be used for output pulse shaping allowing performance improvement over a wide variety
of conditions (The arbitrary pulse generators are available in both T1 and E1). The operation and configuration
of the XRT83L38 can be controlled through a parallel microprocessor Host interface or Hardware control.
MASTER CLOCK GENERATOR
Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or
E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit.
There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are
available these clocks can be connected to the respective pins. All channels of a given XRT83l38 must be
operated at the same clock rate, either T1, E1 or J1 modes.
In systems that have only one master clock source available (E1 or T1), that clock should be connected to both
MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz,
16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according
to
N
OTE
Table
: EQC[4:0] determine the T1/E1 operating mode. See
1.
F
IGURE
F
IGURE
Input Clock Options
2.048MHz
1.544MHz
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
+/-50ppm
+/-50ppm
5. O
1.544MHz
2.048MHz
128kHz
256kHz
16kHz
56kHz
64kHz
4. T
8kHz
NE
WO
I
NPUT
I
NPUT
C
LOCK
C
LOCK
S
Two Input Clock Sources
MCLKE1
MCLKT1
OURCE
S
OURCE
MCLKE1
MCLKT1
One Input Clock Source
Figure
22
Table 5
MCLKOUT
1, Host mode and
MCLKOUT
for details.
Figure
1.544MHz
or
2.048MHz
1.544MHz
or
2.048MHz
2, Hardware mode. The
XRT83L38