MR25H40MDF Everspin Technologies, MR25H40MDF Datasheet - Page 6

• Manufacturer Part Number: MR25H40MDF
• Description: NVRAM 4Mb 3.3V 512Kx8 SPI Pre-Qual Sample MRAM
• Manufacturer: Everspin Technologies

Specifications of MR25H40MDF

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Size: 4 MB
• Organization: 512 K x 8
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Operating Current: 20 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Package / Case: DFN-8
• Maximum Power Dissipation: 0.6 W
• Operating Temperature Range: - 40 C to + 125 C
• Operating Voltage: 3 V to 3.6 V

Everspin Technologies © 2011
SPI COMMUNICATIONS PROTOCOL
Write Status Register (WRSR)
Write Enable (WREN)
Write Disable (WRDI)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a
WREN command while pin WP and bit SRWD correspond to values that make the status register writable
as seen in table 2.3. Status Register bits are non-volatile with the exception of the WEL which is reset to 0
upon power cycling.
The WRSR command is entered by driving CS low, sending the command code and status register write
data byte, and then driving CS high.
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The
Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN
command is entered by driving CS low, sending the command code, and then driving CS high.
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7).
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, send-
ing the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed.
SCK
SCK
CS
SO
SO
SI
CS
SI
Mode 3
Mode 0
Mode 3
Mode 0
0
0
0
0
0
0
Figure 2.2 WREN
1
1
Figure 2.3 WRDI
0
0
High Impedance
High Impedance
2
2
Instruction (06h)
Instruction (04h)
6
0
0
3
3
0
0
4
4
1
1
5
5
1
0
6
6
0
0
7
7
Mode 3
Mode 0
Mode 3
Mode 0
MR25H40 Rev. 5, 11/2011
MR25H40