MR25H40MDF Everspin Technologies, MR25H40MDF Datasheet

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FEATURES • No write delays • Unlimited write endurance • Data retention greater than 20 years • Automatic data protection on power loss • Fast, simple SPI interface with MHz clock rate • 3.0 to 3.6 Volt power supply range • Low current sleep mode • Industrial temperatures • Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant packages. • Direct replacement for serial EEPROM, Flash, FeRAM INTRODUCTION The MR25H40 is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 524,288 words of 8 bits. The MR25H40 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H40 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins. The MR25H40 is available in either 8-pin DFN package 8-pin DFN Small Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products. The MR25H40 provides highly reliable data storage over a wide range of temperatures. The product is offered with industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) operating temperature range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. SPI COMMUNICATIONS PROTOCOL...................................................... 4 ...

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DEVICE PIN ASSIGNMENT Overview The MR25H40 is a serial MRAM with memory array logically organized as 512Kx8 using the four pin inter- face of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral inter- face (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash components allowing MRAM to replace these components in the same socket and interoperate on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and more reliable data retention compared to available serial memory alternatives HOLD SCK SI System Configuration Single or multiple devices can be connected to the bus as show in Figure 1.2. Pins SCK, SO and SI are com- mon among devices. Each device requires CS and HOLD pins to be driven seperately. Everspin Technologies © 2011 Figure 1.1 Block Diagram Instruction Decode Clock Generator Control Logic Write Protect Instruction Register 19 Address Register Counter ...

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DEVICE PIN ASSIGNMENT Signal Name Pin I/O Function CS 1 Input Chip Select SO 2 Output Serial Output WP 3 Input Write Protect V 4 Supply Ground Input Serial Input SCK 6 Input Serial Clock HOLD 7 Input Hold V 8 Supply ...

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SPI COMMUNICATIONS PROTOCOL MR25H40 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. De- pending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Instruction Description WREN Write Enable WRDI Write Disable RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes WRITE Write Data Bytes SLEEP Enter Sleep Mode WAKE Exit Sleep Mode Status ...

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SPI COMMUNICATIONS PROTOCOL WEL SRWD Low 1 1 High Status Register BP1 BP0 Block Protection The memory enters hardware block protection when the WP input is low and the Status Register Write Dis- able (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high. While WP is low, the write protection blocks for the memory are determined by the status register bits BP0 and BP1 and cannot be modified without taking the WP signal high again. If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block write protect bits and this information can be modified using the WRSR command. Read ...

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SPI COMMUNICATIONS PROTOCOL Write Enable (WREN) The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN command is entered by driving CS low, sending the command code, and then driving CS high. CS Mode 3 SCK Mode Write Disable (WRDI) The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7). This prevents writes to status register or memory. The WRDI command is entered by driving CS low, send- ing the command code, and then driving CS high. The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed. CS Mode 3 SCK Mode Write Status Register (WRSR) The Write Status Register (WRSR) command allows new values to be written to the Status Register. The WRSR command is not executed unless the Write Enable Latch (WEL) has been set executing a WREN command while pin WP and bit SRWD correspond to values that make the status register writable ...

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SPI COMMUNICATIONS PROTOCOL CS SCK SI SO Read Data Bytes (READ) The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are read out sequen- tially from memory until the read operation is terminated by bringing CS high The entire memory can be read in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bringing CS high SCK Instruction (03h Everspin Technologies © 2011 Figure 2.4 WRSR ...

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SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-18 are decoded by the memory. The data bytes are written sequen- tially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in mem- ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high SCK Instruction (02h ...

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SPI COMMUNICATIONS PROTOCOL Enter Sleep Mode (SLEEP) The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com- mand code, and then driving CS high. The standby current is achieved after time, t when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid command following SLEEP mode entry is a WAKE command SCK Exit Sleep Mode (WAKE) The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after t WAKE must be executed after sleep mode entry and prior to any other command SCK Everspin Technologies © 2011 Figure ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Parameter Supply voltage 2 Voltage on any pin 2 Output current per pin Package power dissipation Temperature under bias MR25H40C (Industrial) Temperature under bias MR25H40M (AEC-Q100 Grade 1) Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced than 0.5V. The AC value less than 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2011 Table ...

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ELECTRICAL SPECIFICATIONS Parameter Power supply voltage Input high voltage Input low voltage Temperature under bias MR25H40C (Industrial) Temperature under bias MR25H40M (AEC-Q100 Grade 1) AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years 1 out of 20-year life.) Parameter Input leakage current Output leakage current Output low voltage ( mA +100 μA) OL Output high voltage ( mA -100 μA) OH Parameter Active Read Current (@ 1 MHz) Active Read Current (@ 40 MHz) Active Write Current (@ 1 MHz) Active Write Current (@ 40 MHz) AC Standby Current (CS High) CMOS Standby Current (CS High) Standby Sleep Mode Current (CS High) Everspin Technologies © 2011 ...

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TIMING SPECIFICATIONS Parameter Control input capacitance Input/Output capacitance ƒ = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Figure 4.1 Output Load for Impedance Parameter Measurements Output Figure 4.2 Output Load for all Other Parameter Measurements Everspin Technologies © 2011 Table 4.1 Capacitance ...

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TIMING SPECIFICATIONS Power-Up Timing The MR25H40 is not accessible for a start-up time, t from the time when V (min) is reached until the first CS low to allow internal voltage references to become DD stable. The CS signal should be pulled sequence. Parameter Write Inhibit Voltage Startup Time (max (min) DD Reset state of the device V WI Everspin Technologies © 2011 = 400 μs after power up. Users must wait this time PU so that the signal tracks the power supply during power-up DD Table 4.3 Power-Up Symbol Min ...

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TIMING SPECIFICATIONS Synchronous Data Timing Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time Synchronous Data Timing (See figure 4.4) CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Output Valid (Industrial) Output Valid (AEC-Q100 Grade 1) Output Hold Time HOLD Timing (See figure 4.5) HOLD Setup Time HOLD Hold Time HOLD to Output Low Impedance HOLD to Output High Impedance Other Timing Specifications WP Setup To CS Low WP Hold From CS High Sleep Mode Entry Time Sleep Mode Exit Time Output Disable Time Operating Temperature Range Everspin Technologies © 2011 Table ...

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TIMING SPECIFICATIONS CSS V IH SCK High Impedance SCK HOLD SO Everspin Technologies © 2011 Figure 4.4 Synchronous Data Timing ...

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... MR25H40MDCR Serial MRAM 8-DFN AEC-Q100 Grade 1 T&R 1 MR25H40CDF Serial MRAM 8-DFN Small Flag Industrial MR25H40CDFR Serial MRAM 8-DFN Small Flag Industrial T& Serial MRAM 8-DFN Small Flag AEC-Q100 MR25H40MDF 1 Grade Serial MRAM 8-DFN Small Flag AEC-Q100 MR25H40MDFR 1 Grade 1 T&R 1 Preliminary Products: These products are classified as Preliminary until the completion of all qualification tests. The speci- fications in this data sheet are intended to be final but are subject to change. Please check the Everspin web site www. everspin.com for the latest information on product status. Everspin Technologies © 2011 Figure 5.1 Part Numbering System Package Options ...

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MECHANICAL DRAWINGS B Pin 1 Index Dimension Max. 5.10 6.10 1.00 Min. 4.90 5.90 0.90 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2011 Figure 6.1 DFN Package A Detail ...

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MECHANICAL DRAWINGS A B Pin 1 Index C D Dimension Max 5.10 6.10 0.90 Min 4.90 5.90 0.80 NOTE: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be within 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2011 Figure 6.2 DFN Small Flag ...

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... Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci- dental damages. “ ...