DS2155L-DC Maxim Integrated, DS2155L-DC Datasheet - Page 210

• Manufacturer Part Number: DS2155L-DC
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Figure 35-5. Receive-Side 2.048MHz Boundary Timing (Elastic Store
Enabled)
Note 1: RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1.
Note 2: RSYNC is in the output mode (IOCR1.4 = 0).
Note 3: RSYNC is in the input mode (IOCR1.4 = 1).
Note 4: RCHBLK is forced to 1 in the same channels as RSER (see Note 1).
Note 5: The F-bit position is passed through the receive-side elastic store.
Figure 35-6. Transmit-Side D4 Timing
Note 1: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0).
Note 2: TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1).
Note 3: TSYNC in the multiframe mode (IOCR1.2 = 1).
Note 4: TLINK data (Fs bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled through
RCHBLK
RSYSCLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RSER
FRAME#
TSSYNC
RSIG
TSYNC
TSYNC
TSYNC
TLINK
TLCLK
T1TCR1.2.
3
2
4
1
2
3
4
1
1
CHANNEL 31
2
A
CHANNEL 31
B
3
C/A D/B
4
LSB MSB
5
6
7
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CHANNEL 32
8
A
CHANNEL 32
9
B
10
C/A D/B
LSB
11
F
12
5
CHANNEL 1
1
CHANNEL 1
2
3
4
5