DS2155L-DC Maxim Integrated, DS2155L-DC Datasheet - Page 129

• Manufacturer Part Number: DS2155L-DC
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD)
Bits 1 to 5/Unused, must be set to 0 or proper operation
Bit 6/Receive HDLC Mapping Select (RHMS)
Bit 7/Receive HDLC Reset (RHR). Resets the receive HDLC controller and flushes the receive FIFO. Must be
cleared and set again for a subsequent reset.
0 = normal operation; all FISUs are stored in the receive FIFO and reported to the host.
1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without
host intervention.
0 = receive HDLC assigned to channels
1 = receive HDLC assigned to FDL (T1 mode), Sa bits (E1 mode)
0 = normal operation
1 = reset receive HDLC controller and flush the receive FIFO
RHR
7
0
RHMS
H1RC, H2RC
HDLC #1 Receive Control
HDLC #2 Receive Control
31h, 32h
6
0
—
5
0
—
4
0
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—
3
0
—
2
0
—
1
0
RSFD
0
0