DS2155L-DC Maxim Integrated, DS2155L-DC Datasheet - Page 100

• Manufacturer Part Number: DS2155L-DC
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1
channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel
code array.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32)
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
CH16
CH24
CH32
CH8
7
7
7
7
0
0
0
0
CH15
CH23
CH31
CH7
RCICE1
Receive-Channel Idle-Code Enable Register 1
84h
RCICE2
Receive-Channel Idle-Code Enable Register 2
85h
RCICE3
Receive-Channel Idle-Code Enable Register 3
86h
RCICE4
Receive-Channel Idle-Code Enable Register 4
87h
6
0
6
0
6
0
6
0
CH14
CH22
CH30
CH6
5
0
5
0
5
0
5
0
CH13
CH21
CH29
CH5
4
0
4
0
4
0
4
0
100 of 238
CH12
CH20
CH28
CH4
3
0
3
0
3
0
3
0
CH11
CH19
CH27
CH3
2
0
2
0
2
0
2
0
CH18
CH26
CH10
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH1
CH9
0
0
0
0
0
0
0
0