HEF4093BT-Q100 NXP Semiconductors, HEF4093BT-Q100 Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
HEF4093BT-Q100
Manufacturer Part Number
HEF4093BT-Q100
Description
Logic Gates 2-IN NAND Gate 15V
Manufacturer
NXP Semiconductors
Datasheet
1.HEF4093BT-Q100.pdf
(14 pages)
Specifications of HEF4093BT-Q100
Product
NAND
Number Of Gates
4
Number Of Lines (input / Output)
2 /
High Level Output Current
- 2.4 mA
Low Level Output Current
2.4 mA
Supply Voltage - Max
15 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
10 mA
Power Dissipation
500 mW
Part # Aliases
HEF4093BT-Q100,118
NXP Semiconductors
12. Waveforms
Table 9.
Table 10.
HEF4093B_Q100
Product data sheet
Supply voltage
V
5 V to 15 V
Supply voltage
V
5 V to 15 V
Fig 4.
Fig 5.
DD
DD
Measurement points are given in
Logic levels: V
t
Propagation delay and output transition time
Test data given in
Definitions for test circuit:
DUT = Device Under Test.
C
R
Test circuit
r
, t
L
T
Measurement points
Test data
f
= load capacitance including jig and probe capacitance.
= termination resistance should be equal to the output impedance Z
= input rise and fall times.
OL
and V
Table
Input
V
V
OH
10.
I
SS
are typical output voltage levels that occur with the output load.
or V
output
DD
input
Table
Input
V
0.5V
All information provided in this document is subject to legal disclaimers.
G
M
V
V
0 V
OH
OL
9.
V
DD
I
V
10 %
I
Rev. 1 — 12 July 2012
90 %
R T
V
90 %
M
DUT
V
t
r
V
DD
10 %
M
t
PHL
t
t
20 ns
THL
r
, t
f
V
O
C L
o
of the pulse generator.
001aag182
t
f
001aag197
t
PLH
t
TLH
Quad 2-input NAND Schmitt trigger
V
0.5V
Output
M
HEF4093B-Q100
DD
Load
C
50 pF
L
© NXP B.V. 2012. All rights reserved.
6 of 14