HEF4093BT-Q100 NXP Semiconductors, HEF4093BT-Q100 Datasheet - Page 2

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HEF4093BT-Q100

Manufacturer Part Number
HEF4093BT-Q100
Description
Logic Gates 2-IN NAND Gate 15V
Manufacturer
NXP Semiconductors
Datasheet

Specifications of HEF4093BT-Q100

Product
NAND
Number Of Gates
4
Number Of Lines (input / Output)
2 /
High Level Output Current
- 2.4 mA
Low Level Output Current
2.4 mA
Supply Voltage - Max
15 V
Supply Voltage - Min
3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SO-14
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Operating Temperature Range
- 40 C to + 125 C
Output Current
10 mA
Power Dissipation
500 mW
Part # Aliases
HEF4093BT-Q100,118
NXP Semiconductors
5. Functional diagram
6. Pinning information
HEF4093B_Q100
Product data sheet
Fig 1.
Fig 3.
Functional diagram
Pin configuration
1A
1B
2A
2B
3A
3B
4A
4B
6.1 Pinning
1
2
5
6
8
9
12
13
001aag104
10
11
3
4
All information provided in this document is subject to legal disclaimers.
1Y
2Y
3Y
4Y
VSS
1B
1Y
2Y
2B
1A
2A
Rev. 1 — 12 July 2012
HEF4093B-Q100
1
2
3
4
5
6
7
aaa-003547
Fig 2.
14
13
12
11
10
9
8
VDD
4B
4A
4Y
3Y
3B
3A
Logic diagram (one gate)
nA
nB
Quad 2-input NAND Schmitt trigger
HEF4093B-Q100
© NXP B.V. 2012. All rights reserved.
001aag105
nY
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