IDT74ALVCH16901PAG IDT, Integrated Device Technology Inc, IDT74ALVCH16901PAG Datasheet

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IDT74ALVCH16901PAG

Manufacturer Part Number
IDT74ALVCH16901PAG
Description
IC UNIV BUS TXRX 18BIT 64TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74ALVCHr
Datasheet

Specifications of IDT74ALVCH16901PAG

Logic Type
Universal Bus Transceiver, CMOS
Number Of Circuits
18-Bit
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ALVCH16901PAG
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
©2006 Integrated Device Technology, Inc.
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
machine model (C = 200pF, R = 0)
CC
CC
CC
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
= 2.5V ± 0.2V
SK(o)
ODD/EVEN
1
2
CLKENAB
CLKENAB
(Output Skew) < 250ps
1
2
CLKAB
1
1
2
2
A
A
APAR
ERRB
ERRB
OEAB
APAR
LEAB
1
1
SEL
-
-
1
2
A
A
8
8
1
32
3
30
5
61
28
36
2
34
31
Generate
B Data
A-Port
Check
Parity
3.3V CMOS 18-BIT
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
and
18
18
2
Q
B
Storage
Storage
18-Bit
18-Bit
1
DESCRIPTION:
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs
for checking parity. The direction of data flow is controlled by OEAB and
OEBA. When SEL is low, the parity functions are enabled. When SEL is high,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
This 18-bit universal bus transceiver is built using advanced dual metal
The ALVCH16901 features independent clock (CLKAB or CLKBA),
The ALVCH16901 has been designed with a ±24mA output driver. This
The ALVCH16901 has “bus-hold” which retains the inputs’ last state
Q
A
18
18
2
Generate
A Data
B-Port
Check
Parity
and
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16901
37
29
35
60
62
64
33
63
4
1
CLKBA
OEBA
1
1
2
2
1
2
LEBA
2
B
BPAR
ERRA
CLKENBA
CLKENBA
B
BPAR
ERRA
1
1
-
-
1
2
B
A
8
8
March 2006
DSC-4582/3

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IDT74ALVCH16901PAG Summary of contents

Page 1

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R ...

Page 2

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY PIN CONFIGURATION 1 CLKENAB 1 2 LEAB 3 CLKAB 4 ERRA 1 APAR 5 1 GND ...

Page 3

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY FUNCTION TABLE (1,2) Inputs CLKENAB OEAB LEAB CLKAB ...

Page 4

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW ...

Page 5

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the ...

Page 6

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY SWITCHING CHARACTERISTICS Symbol Parameter f MAX t Propagation Delay PLH t xAx to xBx or xBx to xAx PHL t Propagation Delay PLH t xAx to xBPAR or xBx to xAPAR ...

Page 7

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY SWITCHING CHARACTERISTICS (CONTINUED) Symbol Parameter t Output Enable Time PZH OEAB or OEBA to xBx, xBPAR or xAx, xAPAR t PZL t Output Enable Time PZH OEAB or OEBA to xERRA ...

Page 8

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 ...

Page 9

IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY ORDERING INFORMATION XX ALVC X XXX Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XXX XX Package Device Type PA PAG 901 16 H ...

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