XRT83L314ES Exar, XRT83L314ES Datasheet - Page 71

• Manufacturer Part Number: XRT83L314ES
• Description: LIN Transceivers
• Manufacturer: Exar

Specifications of XRT83L314ES

• Product Category: LIN Transceivers
• Rohs: yes

B
D7
D6
D5
D4
D3
D2
D1
D0
IT
LCV/OFLW Line Code Violation / Counter Overflow Monitor Select
CNTRDEN Line Code Violation Counter Read Enable
Reserved
Reserved
LCVCH3
LCVCH2
LCVCH1
LCVCH0
N
AME
T
ABLE
This bit is used to select the monitoring activity between the LCV
and the counter overflow status. When the 16-bit LCV counter sat-
urates, the counter overflow condition is activated. By default, the
LCV activity is monitored by bit D4 in register 0x05h.
0 = Monitoring LCV
1 = Monitoring the counter overflow status
This bit enables the 16-bit LCV counter contents to be read from
bits D[7:0] in register 0xE8h. If a counter reaches full scale, it sat-
urates and remains at FFFFh until a reset is initiated in register
0xE6h. By default the LCV counter readback function is disabled.
0 = Disabled
1 = Enables the 16-bit LCV Counters for Readback
This Register Bit is Not Used
This Register Bit is Not Used
Line Code Violation Counter Select
These bits are used to select which channel is to be addressed for
reading the contents in register 0xE8h. It is also used to address
the counter for a given channel when performing an update or
reset on a per channel basis. By default, Channel 0 is selected.
0000 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0101 = Channel 4
0110 = Channel 5
0111 = Channel 6
1000 = Channel 7
1001 = Channel 8
1010 = Channel 9
1011 = Channel 10
1100 = Channel 11
1101 = Channel 12
1110 = Channel 13
46: M
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
ICROPROCESSOR
G
LOBAL
R
F
UNCTION
EGISTER
R
67
EGISTER
(0
X
E5
0
X
H
E5
)
H
B
IT
D
ESCRIPTION
Register
Type
R/W
R/W
R/W
R/W
R/W
XRT83L314
(HW reset)
Default
REV. 1.0.0
Value
0
0
0
0
0