XRT83L314ES Exar, XRT83L314ES Datasheet - Page 4

• Manufacturer Part Number: XRT83L314ES
• Description: LIN Transceivers
• Manufacturer: Exar

Specifications of XRT83L314ES

• Product Category: LIN Transceivers
• Rohs: yes

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION.............................................................................................................. 1
PIN OUT OF THE XRT83L314........................................................................................................ 3
T
PIN DESCRIPTIONS....................................................................................................................... 3
1.0 CLOCK SYNTHESIZER .......................................................................................................................13
2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................14
ABLE OF
F
T
F
F
F
T
F
T
F
F
F
T
F
F
F
T
F
F
F
T
F
F
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
APPLICATIONS .......................................................................................................................................................... 1
FEATURES
PRODUCT ORDERING INFORMATION ..................................................................................................2
M
R
T
C
C
P
N
1.1 ALL T1/E1 MODE ........................................................................................................................................... 14
2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 15
2.2 EQUALIZER CONTROL ................................................................................................................................. 17
2.3 CABLE LOSS INDICATOR ............................................................................................................................. 17
2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 18
2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 18
2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 19
2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24
2.8 HDB3/B8ZS DECODER .................................................................................................................................. 24
2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 25
RANSMITTER
OWER AND
ECEIVER
ONTROL
LOCK
O
ICROPROCESSOR
C
1: I
2: S
3: S
4: S
5: T
6: A
2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 15
2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 16
2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20
2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 21
2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21
1. B
2. S
3. S
4. T
5. T
6. S
7. S
8. S
9. R
10. R
11. T
12. T
13. I
14. A
15. P
16. S
ONNECTS
S
NPUT
IMING
ELECTING THE
ELECTING THE
ELECTING THE
NALOG
ECTION
C
YPICAL
2.6.3.1 RLOS (R
2.6.3.2 EXLOS (E
2.6.3.3 AIS (A
2.6.3.4 NLCD (N
2.6.3.5 FLSD (FIFO L
2.6.3.6 LCV/OFD (L
LOCK
IMPLIFIED
IMPLIFIED
IMPLIFIED
ECEIVE
NTERRUPT
YPICAL
F
IMPLIFIED
IMPLIFIED
..................................................................................................................................................................... 2
S
EST
EST
NALOG
ROCESS
INGLE
ECEIVE
ONTENTS
UNCTION
ECTION
G
C
S
S
LOCK
ROUND
C
C
D
RLOS D
............................................................................................................................................................ 12
PECIFICATIONS FOR
ECTION
C
ONFIGURATION FOR
ONFIGURATION FOR
IAGRAM OF THE
............................................................................................................................................................ 9
D
R
C
R
ONNECTION
D
AIL
ATA
ONNECTION
B
B
B
B
ECEIVE
B
B
........................................................................................................................................................ 3
ATA
S
G
....................................................................................................................................................... 4
LOCK
LOCK
LOCK
LOCK FOR
...................................................................................................................................................... 9
LOCK
LOCK
OURCE
M
ENERATION
I
V
S
.................................................................................................................................................. 10
U
NTERNAL
LARM
ECLARE
ODE
ALUE OF THE
LICER
U
.................................................................................................................................................. 7
PDATED ON THE
PDATED ON THE
............................................................................................................I
D
D
D
ECEIVER
ETWORK
D
D
L
XTENDED
IAGRAM OF THE
IAGRAM OF THE
IAGRAM OF THE
OS OF
W
IAGRAM OF THE
IAGRAM OF THE
S
D
I
INE
L
NDICATION
D
ELECT
ITH A
A
EVEL FOR THE
/C
IAGRAM
IMIT
XRT83L314 .................................................................................................................................... 1
IAGRAM
I
UTOMATIC
MPEDANCE
C
P
LEAR
S
RCLK/RPOS/RNEG................................................................................................................. 20
L
ROCESS
L
ODE
M
M
S
IGNAL FOR
F
OSS OF
OOP
.............................................................................................................................................. 13
E
L
TATUS
IXED
EASURING
EASURING
XTERNAL
OSS OF
(T
U
V
U
R
SING
YPICAL
S
C
IOLATION
F
SING
TABLE OF CONTENTS
ISING
L
R
IGNAL
ALLING
ODE
.................................................................................................................................... 15
E
C
E
B
C
R
OOP
EPEATING
S
D
QUALIZER AND
QUALIZER
ABLE
LOCK
P
LOCK
ECEIVE
IGNAL
ETECTION
O
S
I
T1/E1/J1................................................................................................................ 22
EAK
NTERNAL
F
E
D
IGNAL
NE
R
I
V
NTERFERENCE
) ......................................................................................................................... 22
C
IXED
DGE OF
ETECTION
ECEIVE
ALUES
E
ODE
L
......................................................................................................................... 21
/ C
S
E
D
) ..................................................................................................................... 21
OSS
DGE OF
XTERNAL
YNTHESIZER
P
ETECTOR
) .................................................................................................................. 22
OUNTER
R
"0011" P
ATH
A
D
) ............................................................................................................... 24
ESISTOR
)
I
TTENUATION
T
ETECTION
NDICATOR
RCLK..................................................................................................... 19
S
FOR
ERMINATION
ENSITIVITY
) .......................................................................................................... 22
............................................................................................................ 14
P
RCLK................................................................................................. 19
EAK
F
T1/E1 ............................................................................................. 22
....................................................................................................... 18
O
M
ATTERN
IXED
I
.................................................................................................... 16
VERFLOW
................................................................................................... 14
ARGIN
D
................................................................................................ 17
................................................................................................ 23
ETECTOR
R
F
............................................................................................ 20
ESISTOR
LAG
.......................................................................................... 15
......................................................................................... 21
......................................................................................... 25
D
.................................................................................... 18
ETECTION
................................................................................. 17
.............................................................................. 16
) ................................................................. 24