XRT83L314ES Exar, XRT83L314ES Datasheet - Page 62

• Manufacturer Part Number: XRT83L314ES
• Description: LIN Transceivers
• Manufacturer: Exar

Specifications of XRT83L314ES

• Product Category: LIN Transceivers
• Rohs: yes

XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
N
OTE
B
: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
D7
D6
D5
D4
D3
IT
interrupt pin.
EQFLAG
LCV/OF
NLCD
N
DMO
FLS
AME
T
ABLE
Equalizer Attenuation Flag
The equalizer attenuation flag is always active regardless if the
interrupt generation is disabled. This bit indicates the EQFLAG
activity. An interrupt will not occur unless the EQFLAGE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = Equalizer Attenuation Flag is Set
Digital Monitor Output
The digital monitor output is always active regardless if the inter-
rupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the chan-
nel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Transmit output driver has failures
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0x04h and GIE is set to
"1" in the global register 0xE0h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0xE5h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV/OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
Network Loop Code Detection
The network loop code detection is always active regardless if the
interrupt generation is disabled. This bit indicates the NLCD activ-
ity. An interrupt will not occur unless the NLCDIE is set to "1" in the
channel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Network loop code detected according to the mode selected in
channel register 0x03h
30: M
ICROPROCESSOR
C
HANNEL
0-13 (0
F
UNCTION
R
58
EGISTER
X
05
H
-0
0
X
D5
X
05
H
)
H
B
IT
D
ESCRIPTION
Register
Type
RO
RO
RO
RO
RO
(HW reset)
Default
Value
0
0
0
0
0