E910.54B37AB ELMOS Semiconductor, E910.54B37AB Datasheet - Page 14

• Manufacturer Part Number: E910.54B37AB
• Description: Interface - Specialized FlexRay Transceiver
• Manufacturer: ELMOS Semiconductor

Specifications of E910.54B37AB

• Rohs: yes
• Product Type: FlexRay Transceiver
• Operating Supply Voltage: 5 V
• Supply Current: 50 mA
• Maximum Power Dissipation: 150 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-14
• Minimum Operating Temperature: - 40 C

4.2.2.3 Power-on
The Power-on provides the power on reset signal after switch on of VCC.
4.2.3 communication controller interface
The interface concerns the pins TxEN, TxD and RxD. TxEN (low active) enables the transmit function. The TxD from
the CC is an input signal of the transceiver. The line drivers of the transmitter send a balanced differential signal to
the bus lines according to the TxD signal. The receiver recognizes the bus states Data_1, Data_0 and Idle. It trans-
forms the differential bus voltage uBus to the digital signal at VIO level at the output pin RxD.
4.2.4 Host interface
Diagnosis information of the transceiver and the bus (overload, underload, short circuits, undervoltages and over-
temperature) are stored in a register block. The data transfer to the host is accomplished by means of a SPI inter-
face. Supported modes and bit order are shown in fig. 8. With this mode the output shift operation always takes
place before the input sample operation. The clock polarity is fix CPOL = 0. The MSB is always transmitted / re-
ceived first. Two bytes are transmitted within one SPI access. The shift out is done at the rising edge of SCK, the
shift in at the falling edge of SCK.
Figure 8: E910.54 SPI communication cycle
There is a minimum time span dspis between the falling edge of SCSN and the start of the first clock (rising edge).
Also a minimum time dspih after the last (16th) clock (falling edge) and the rising edge of SCSN is defined. The nec-
essary time of the internal processing between two SPI accesses is dspid.
For an efficient register access, a protocol has been defined with the following features:
• Pure master-slave protocol with host controller as master
• Frame is delimited by the status of SCSN (SCSN = frame delimiter)
ELMOS Semiconductor AG
scsn
sDO
scK
sDi
float
X
dspis
X
MSB
1
sample ( BD )
MSB
sample ( host)
14
16 clocks /cycle
2
14
13
Data sheet
3
14/28
13
12
4
12
1
15
1
LSB
16
LSB
QM-No.: 25DS0004.00 2010-02-03
dspih
X
float
E910.54