C8051F343-GMR Silicon Labs, C8051F343-GMR Datasheet - Page 252
![no-image](/images/no-image-200.jpg)
C8051F343-GMR
Manufacturer Part Number
C8051F343-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 32KB 10 ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F349-GMR.pdf
(276 pages)
Specifications of C8051F343-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 252 of 276
- Download datasheet (2Mb)
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
When T3SPLIT = ‘1’, the Timer 3 registers (TMR3H and TMR3L) act as two 8-bit counters. Each counter
counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-
tents of the Timer 3 registers are latched into the Timer 3 Reload registers (TMR3RLH and TMR3RLL). A
Timer 3 interrupt is generated if enabled.
252
External Clock / 8
SYSCLK / 12
H
T
F
3
T
F
3
L
TMR3CN
T
F
3
L
E
N
C
T
3
E
S
P
T
3
L
T
I
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)
T
R
3
T
3
C
S
S
C
T
3
X
L
K
0
1
SYSCLK
0
1
1
0
T
M
H
3
M
T
3
L
CKCON
M
H
T
2
M
T
2
L
TR3
T
M
1
M
T
0
Rev. 1.3
C
S
A
1
USB Start-of-Frame (SOF)
S
C
A
0
Low-Frequency Oscillator
TCLK
TCLK
Falling Edge
TMR3RLH
TMR3RLL
TMR3H
TMR3L
Capture
Capture
To ADC
T3CSS
0
1
Enable
Interrupt
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