C8051F343-GMR Silicon Labs, C8051F343-GMR Datasheet - Page 152
![no-image](/images/no-image-200.jpg)
C8051F343-GMR
Manufacturer Part Number
C8051F343-GMR
Description
8-bit Microcontrollers - MCU 48 MIPS 32KB 10 ADC
Manufacturer
Silicon Labs
Datasheet
1.C8051F349-GMR.pdf
(276 pages)
Specifications of C8051F343-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
152
Bits7–0: P1.[7:0]
Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively).
Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in regis-
P1.7
R/W
R/W
R/W
Bit7
Bit7
Bit7
Write - Output appears on I/O pins per Crossbar Registers (when XBARE = ‘1’).
0: Logic Low Output.
1: Logic High Output (high impedance if corresponding P1MDOUT.n bit = 0).
Read - Always reads ‘0’ if selected as analog input in register P1MDIN. Directly reads Port
pin when configured as digital input.
0: P1.n pin is logic low.
1: P1.n pin is logic high.
Port pins configured as analog inputs have their weak pull-up, digital driver, and digital
receiver disabled.
0: Corresponding P1.n pin is configured as an analog input.
1: Corresponding P1.n pin is not configured as an analog input.
ter P1MDIN is logic 0.
0: Corresponding P1.n Output is open-drain.
1: Corresponding P1.n Output is push-pull.
P1.6
R/W
R/W
R/W
Bit6
Bit6
Bit6
SFR Definition 15.10. P1MDOUT: Port1 Output Mode
SFR Definition 15.9. P1MDIN: Port1 Input Mode
P1.5
R/W
R/W
R/W
Bit5
Bit5
Bit5
SFR Definition 15.8. P1: Port1 Latch
P1.4
R/W
R/W
R/W
Bit4
Bit4
Bit4
Rev. 1.3
P1.3
R/W
R/W
R/W
Bit3
Bit3
Bit3
P1.2
R/W
R/W
R/W
Bit2
Bit2
Bit2
P1.1
R/W
R/W
R/W
Bit1
Bit1
Bit1
(bit addressable)
P1.0
R/W
R/W
R/W
Bit0
Bit0
Bit0
SFR Address:
SFR Address:
SFR Address:
00000000
Reset Value
Reset Value
Reset Value
11111111
11111111
0x90
0xF2
0xA5
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