C8051F303-GSR Silicon Labs, C8051F303-GSR Datasheet - Page 68
![no-image](/images/no-image-200.jpg)
C8051F303-GSR
Manufacturer Part Number
C8051F303-GSR
Description
8-bit Microcontrollers - MCU 8KB 14Pin MCU
Manufacturer
Silicon Labs
Datasheet
1.C8051F301-GSR.pdf
(178 pages)
Specifications of C8051F303-GSR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
- Current page: 68 of 178
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C8051F300/1/2/3/4/5
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
68
TH1
TL0
TL1
TMOD
TMR2RLH
TMR2RLL
TMR2H
TMR2L
XBR0
XBR1
XBR2
0x97, 0xAE, 0xAF, 0xB4,
0xB6, 0xBF, 0xCE, 0xD2,
0xD3, 0xD4, 0xD5, 0xD6,
0xD7, 0xDD, 0xDE, 0xDF,
0xF5
*Note: SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Bits7–0: DPL: Data Pointer Low.
Register
R/W
Bit7
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W
Bit6
Address
0xCB
0xCA
0xCD
0xCC
0x8D
0x8A
0x8B
0x89
0xE1
0xE2
0xE3
Table 8.3. Special Function Registers* (Continued)
SFR Definition 8.1.
R/W
Bit5
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 2 High
Timer/Counter 2 Low
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
Reserved
R/W
Bit4
DPL: Data Pointer Low Byte
Rev. 2.9
R/W
Bit3
Description
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x82
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