C8051F540-IQR Silicon Labs, C8051F540-IQR Datasheet - Page 109

• Manufacturer Part Number: C8051F540-IQR
• Description: 8-bit Microcontrollers - MCU 50 MIPS 16 kB 1 kB LIN 2.1 SPI
• Manufacturer: Silicon Labs

Specifications of C8051F540-IQR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

SFR Definition 13.1. IE: Interrupt Enable
SFR Address = 0xA8; Bit-Addressable; SFR Page = All Pages
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ESPI0
Name
ET2
ES0
ET1
EX1
ET0
EX0
EA
R/W
EA
7
0
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
ESPI0
R/W
6
0
R/W
ET2
5
0
ES0
R/W
Rev. 1.1
4
0
Function
R/W
ET1
3
0
EX1
R/W
2
0
C8051F54x
R/W
ET0
1
0
EX0
R/W
0
0
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