C8051F540-IQR Silicon Labs, C8051F540-IQR Datasheet - Page 92
C8051F540-IQR
Manufacturer Part Number
C8051F540-IQR
Description
8-bit Microcontrollers - MCU 50 MIPS 16 kB 1 kB LIN 2.1 SPI
Manufacturer
Silicon Labs
Datasheet
1.C8051F546-IMR.pdf
(274 pages)
Specifications of C8051F540-IQR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F54x
SFR Page 0x00
Automatically
pushed on stack in
SFRPAGE on SPI0
interrupt
0x00
SFRPAGE
(SPI0)
SFRPAGE
pushed to
0x0F
SFRNEXT
SFRNEXT
(SMB0ADR)
SFRLAST
Figure 12.3. SFR Page Stack After SPI0 Interrupt Occurs
While in the SPI0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the SPI0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x00 for SPI00) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x0F for SMB0ADR) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be
overwritten. See Figure 12.4.
92
Rev. 1.1
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