MAX11014BGTM+ Maxim Integrated, MAX11014BGTM+ Datasheet - Page 35

• Manufacturer Part Number: MAX11014BGTM+
• Description: Special Purpose Amplifiers Auto RF MESFET Amp Drain-Current Cntrlr
• Manufacturer: Maxim Integrated
• Series: MAX11014, MAX11015r

Specifications of MAX11014BGTM+

• Rohs: yes
• Common Mode Rejection Ratio (min): 90 dB
• Operating Supply Voltage: 0.5 V to 11 V
• Supply Current: 2.8 mA
• Maximum Power Dissipation: 2162.2 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-48
• Available Set Gain: 13.98 dB

Select each channel’s maximum GATE voltage, clock
mode, ADC monitoring, DAC and ADC reference
modes by setting bits D11–D0 in the hardware configu-
ration register. Set the command byte to 38h to write to
the hardware configuration register. Set the command
byte to B8h to read from the hardware configuration
register. Bits D15–D12 are don’t care. Set the
CH2OCM1/0 bits, D11 and D10, to determine the maxi-
mum positive GATE2 output voltage. Set the
CH1OCM1/0 bits, D9 and D8, to determine the maxi-
mum positive GATE1 output voltage. See Table 10.
Set the ADCMON bit, D6, to 1 to load the ADC results
into the FIFO. Set ADCMON to 0 to not load ADC
results into the FIFO. Set the CKSEL1/0 bits, D5 and
D4, to determine the conversion and acquisition timing
clock modes. See Table 10b. Also, see the Internally
Timed Acquisitions and Conversions and the Externally
Table 9. VL1 and VL2 (Read/Write)
X = Don’t care.
Table 10. HCFG (Read/Write)
RESET
STATE
BIT VALUE
BIT NAME
CH2OCM1
CH2OCM0
CH1OCM1
CH1OCM0
ADCMON
ADCREF1
ADCREF0
DACREF1
DACREF0
BIT
CKSEL1
CKSEL0
X
X
D15
X
X
______________________________________________________________________________________
D14
DATA BIT
X
X
D15–D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
X
X
HCFG (Read/Write)
D12
X
X
RESET STATE
Automatic RF MESFET Amplifier
MSB
D11
0
X
0
0
0
0
X
0
0
0
0
0
0
0
D10
—
0
Don’t care.
Maximum GATE2 voltage control bits.
Maximum GATE1 voltage control bits.
Don’t care.
ADC monitor bit. Set to 1 to load ADC results into the FIFO. Set to 0 to not
load any ADC results into the FIFO. The value of ADCMON does NOT
affect whether the results from any particular ADC conversion are
checked against ALARM limits or examined for changes to the
V
Clock mode and CNVST configuration bits.
ADC reference select bits.
DAC reference select bits.
DAC(CODE)
D9
—
0
Drain-Current Controllers
D8
—
0
Timed Acquisitions and Conversions sections. Set the
ADCREF1/0 bits, D3 and D2, to determine the ADC ref-
erence source. See Table 10c. Set the DACREF1/0 bits,
D1 and D0, to determine the DAC reference source.
See Table 10d.
Write to the software configuration register to determine
whether a V
the DAC input register or DAC input and output regis-
ter. This register also sets the control modes for the K
parameter and temperature lookup values in the
V
to write to the software configuration register. Set the
command byte to BAh to read from the software config-
uration register.
DAC(CODE)
equations.
D7
—
0
D6
—
DAC(CODE)
0
calculation. Set the command byte to 3Ah
FUNCTION
D5
—
0
calculation value is loaded to
D4
—
0
D3
—
0
SCFG (Read/Write)
D2
—
0
D1
—
0
LSB
D0
0
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