MAX11014BGTM+ Maxim Integrated, MAX11014BGTM+ Datasheet - Page 32

• Manufacturer Part Number: MAX11014BGTM+
• Description: Special Purpose Amplifiers Auto RF MESFET Amp Drain-Current Cntrlr
• Manufacturer: Maxim Integrated
• Series: MAX11014, MAX11015r

Specifications of MAX11014BGTM+

• Rohs: yes
• Common Mode Rejection Ratio (min): 90 dB
• Operating Supply Voltage: 0.5 V to 11 V
• Supply Current: 2.8 mA
• Maximum Power Dissipation: 2162.2 mW
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-48
• Available Set Gain: 13.98 dB

The MAX11014/MAX11015 communicate between the
internal registers and external bus lines through the serial
interface. Table 1 details the command bits (C7–C0) and
the data bits (D15–D0) of the serial input word. Table 2
Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 2. Register Listing (see Appendix: Startup Code Example for sample startup
sequence)
32
ADC Conversion
ALARM Flag Register
Channel 1 DAC Input
Channel 1 DAC Input and Output
Channel 1 High GATE Voltage ALARM Threshold
Channel 1 High Sense Voltage ALARM Threshold
Channel 1 High Temperature ALARM Threshold
Channel 1 K Parameter
Channel 1 Low GATE Voltage ALARM Threshold
Channel 1 Low Sense Voltage ALARM Threshold
Channel 1 Low Temperature ALARM Threshold
Channel 1 V
Channel 2 DAC Input
Channel 2 DAC Input and Output
Channel 2 High GATE Voltage ALARM Threshold
Channel 2 High Sense Voltage ALARM Threshold
Channel 2 High Temperature ALARM Threshold
Channel 2 K Parameter
Channel 2 Low GATE Voltage ALARM Threshold
Channel 2 Low Sense Voltage ALARM Threshold
Channel 2 Low Temperature ALARM Threshold
Channel 2 V
First-In First-Out Memory
Flag Register
Hardware ALARM Configuration
Hardware Configuration
LUT Address
LUT Data
PGA Calibration Control
Shutdown
Software ALARM Configuration
Software Clear
Software Configuration
Software Load DAC
______________________________________________________________________________________
SET
SET
REGISTER DESCRIPTION
Register Descriptions
MNEMONIC
THRUDAC1
THRUDAC2
ALMHCFG
ALMSCFG
ALMFLAG
ADCCON
PGACAL
LUTADD
LUTDAT
IPDAC1
IPDAC2
USRK1
USRK2
VSET1
VSET2
HCFG
SCFG
LDAC
FLAG
SHUT
SCLR
FIFO
details the command byte and the subsequent register
accessed. Tables 3–27 detail the various read and write
internal registers and their power-on reset states.
On power-up, the MAX11014/MAX11015 are in full
power-down mode (see the SHUT (Write) section). To
VH1
TH1
VH2
TH2
VL1
VL2
IH1
TL1
IH2
TL2
IL1
IL2
WRITE
4A
2A
4C
2C
3C
7A
7C
3A
62
48
28
24
20
44
26
22
40
4E
34
30
46
36
32
2E
42
38
5E
64
3E
74
66
—
—
—
HEX CODE
READ
AA
AC
AE
BC
FC
BE
BA
A8
A4
A0
A6
A2
B4
B0
B6
B2
B8
—
F8
—
—
—
—
—
—
—
—
80
F6
—
—
—
—
—