PCA9539APW,118 NXP Semiconductors, PCA9539APW,118 Datasheet - Page 9

• Manufacturer Part Number: PCA9539APW,118
• Description: Interface - I/O Expanders 16bit I2C IO Port
• Manufacturer: NXP Semiconductors

Specifications of PCA9539APW,118

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
7. Bus transactions
PCA9539A
Product data sheet
6.5 RESET input
6.6 Interrupt output
7.1 Writing to the port registers
The RESET input can be asserted to initialize the system while keeping the V
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of t
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the ports can be changed externally or through the master. This input requires a
pull-up resistor to V
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time t
changes back to the original value or when data is read form the port that generated the
interrupt (see
or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the
resetting of the interrupt during this pulse. Any change of the I/Os after resetting is
detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
The INT output has an open-drain structure and requires pull-up resistor to V
The PCA9539A is an I
PCA9539A through write and read commands using I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
Data is transmitted to the PCA9539A by sending the device address and setting the least
significant bit to a logic 0 (see
is sent after the address and determines which register will receive the data following the
command byte.
Eight registers within the PCA9539A are configured to operate as four register pairs. The
four pairs are input port, output port, polarity inversion, and configuration registers. After
sending data to one register, the next data byte is sent to the other register in the pair (see
Figure 7
the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
and
v(INT)
w(rst)
Figure
Figure
, the signal INT is valid. The interrupt is reset when data on the port
All information provided in this document is subject to legal disclaimers.
. The PCA9539A registers and I
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8). For example, if the first byte is sent to Output Port 1 (register 3),
10). Resetting occurs in the Read mode at the acknowledge (ACK)
Rev. 1 — 26 September 2012
2
if no active connection is used.
C-bus slave device. Data is exchanged between the master and
Low voltage 16-bit I
Figure 4 “PCA9539A device
2
C-bus I/O port with interrupt and reset
2
C-bus/SMBus state machine are
2
C-bus. The two communication
address”). The command byte
PCA9539A
© NXP B.V. 2012. All rights reserved.
DD
DD
.
at its
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