PCA9539APW,118 NXP Semiconductors, PCA9539APW,118 Datasheet - Page 7

• Manufacturer Part Number: PCA9539APW,118
• Description: Interface - I/O Expanders 16bit I2C IO Port
• Manufacturer: NXP Semiconductors

Specifications of PCA9539APW,118

• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders

NXP Semiconductors
PCA9539A
Product data sheet
6.2.3 Output port register pair (02h, 03h)
6.2.4 Polarity inversion register pair (04h, 05h)
6.2.5 Configuration register pair (06h, 07h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1
Table 7.
Table 8.
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in
Table 9.
Table 10.
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in
read is described in
Table 11.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Output port 0 register (address 02h)
Output port 1 register (address 03h)
Polarity inversion port 0 register (address 04h)
Polarity inversion port 1 register (address 05h)
Configuration port 0 register (address 06h)
and a register pair read is described in
O0.7
O1.7
N0.7
N1.7
C0.7
7
1
7
1
7
0
7
0
7
1
All information provided in this document is subject to legal disclaimers.
Section
Section 7.1
Rev. 1 — 26 September 2012
O0.6
O1.6
N0.6
N1.6
C0.6
6
1
6
1
6
0
6
0
6
1
Low voltage 16-bit I
7.2.
O0.5
O1.5
and a register pair read is described in
N0.5
N1.5
C0.5
5
1
5
1
5
0
5
0
5
1
O0.4
O1.4
N0.4
N1.4
C0.4
4
1
4
1
4
0
4
0
4
1
2
C-bus I/O port with interrupt and reset
Section
O0.3
O1.3
N0.3
N1.3
C0.3
3
1
3
1
3
0
3
0
3
1
Section 7.1
7.2.
O0.2
O1.2
N0.2
N1.2
C0.2
2
1
2
1
2
0
2
0
2
1
PCA9539A
© NXP B.V. 2012. All rights reserved.
and a register pair
Section
O0.1
O1.1
N0.1
N1.1
C0.1
1
1
1
1
1
0
1
0
1
1
7.2.
O0.0
O1.0
N0.0
N1.0
C0.0
0
1
0
1
0
0
0
0
0
1
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