GLS85LP1008B-M-C-LFTE (rev. CB1) Greenliant, GLS85LP1008B-M-C-LFTE (rev. CB1) Datasheet - Page 7

• Manufacturer Part Number: GLS85LP1008B-M-C-LFTE (rev. CB1)
• Description: Flash 8G MLC, NAND MLC 3.3V Comm
• Manufacturer: Greenliant

Specifications of GLS85LP1008B-M-C-LFTE (rev. CB1)

• Product Category: Flash
• Rohs: yes

8 GByte NANDrive
GLS85LP1008B
©2010 Greenliant Systems, Ltd.
Symbol
Host Side Interface
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DMACK#
DMARQ
CS1FX#
CS3FX#
CSEL
IORD#
IOWR#
Table 1: Pin Assignments (1 of 2)
91-LBGA
Pin No.
K8
K3
H8
G9
G8
H7
E8
H4
E3
H3
G3
G2
K2
H2
H9
L2
F9
F8
F7
F4
F3
F2
L3
L8
L9
J3
Type
Pin
I/O
O
I
I
I
I
I
I
I1Z/O2 D[15:0] Data bus
Type Name and Functions
I2U
I1U
I1Z
I2Z
I2Z
I2Z
I/O
O2
A[2:0] are used to select one of eight registers in the Task File.
DMA Acknowledge - input from host
DMA Request to host
CS1FX# is the chip select for the task file registers
CS3FX# is used to select the alternate status register and the Device
Control register.
This internally pulled-up signal is used to configure this device as a
Master or a Slave. When this pin is grounded, this device is configured
as a Master. When the pin is open, this device is configured as a Slave.
The pin setting should remain the same from Power-on to Power-down.
IORD#: This is an I/O Read Strobe generated by the host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device. (This pin supports three functions)
HDMARDY#: In Ultra DMA mode when DMA Read is active, this signal
is asserted by the host to indicate that the host is ready to receive Ultra
DMA data-in bursts. The host may negate HDMARDY# to pause an
Ultra DMA transfer.
HSTROBE: When DMA Write is active, this signal is the data-out strobe
generated by the host. Both the rising and falling edges of HSTROBE
cause data to be latched by the device. The host may stop generating
HSTROBE edges to pause an Ultra DMA data-out burst.
IOWR#: This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into
the device. (This pin supports two functions)
STOP: When Ultra DMA mode protocol is active, the assertion of this
signal causes the termination of the Ultra DMA burst
7
Advance Information
S71421-02-000
05/10