IS25LD020-JVLE-TR ISSI, IS25LD020-JVLE-TR Datasheet - Page 18

• Manufacturer Part Number: IS25LD020-JVLE-TR
• Description: Flash 2M 2.3-3.6V 100Mhz Serial Flash
• Manufacturer: ISSI

Specifications of IS25LD020-JVLE-TR

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 2 Mbit
• Architecture: Uniform
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Current: 15 mA
• Operating Temperature: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Package / Case: VVSOP-8
• Organization: 256 K x 8

DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on two
output pins each at up to a 100 MHz clock.
The FRDO instruction code is followed by three address
bytes (A23 - A0) and a dummy byte (8 clocks), transmitted
via the SI line, with each bit latched-in during the rising edge
of SCK. Then the first data byte addressed is shifted out on
the SO and SIO lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK.
Figure 14. Fast Read Dual-Output Sequence
Integrated Silicon Solution, Inc.- www.issi.com
Rev. D
2/12/2013
SCK
SCK
CE#
CE#
SIO
SIO
SO
SO
32
HIGH IMPEDANCE
33
34
0
HIGH IMPEDANCE
INSTRUCTION = 0011 1011b
35
1
36
2
37
3
38
4
39
5
40
7
6
6
DATA OUT 1
41
7
5
4
The first bit (MSb) is output on SO, while simultaneously the
second bit is output on SIO.
The first byte addressed can be at any memory location. The
address is automatically incremented after each byte of data
is shifted out. When the highest address is reached, the
address counter will roll over to the 000000h address,
allowing the entire memory to be read with a single FRDO
instruction. FRDO instruction is terminated by driving CE#
high (VIH).
42
23
3
2
8
43
22 21
9
0
1
3 - BYTE ADDRESS
10
44
6
7
DATA OUT 2
11
45 46
5
4
...
...
28
3
2
3
47
2
29
1
0
IS25CD512/010
48
30
7
6
1
31
0
IS25LD020
18