AT25DL081-MHN-Y Adesto Technologies, AT25DL081-MHN-Y Datasheet - Page 44
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AT25DL081-MHN-Y
Manufacturer Part Number
AT25DL081-MHN-Y
Description
Flash 8M 1.65-1.95V 100Mhz Serial Flash
Manufacturer
Adesto Technologies
Datasheet
1.AT25DL081-MHN-T.pdf
(59 pages)
Specifications of AT25DL081-MHN-Y
Rohs
yes
Data Bus Width
8 bit
Memory Type
Flash
Memory Size
8 Mbit
Architecture
Flexible, Uniform Erase
Timing Type
Synchronous
Interface Type
SPI
Supply Voltage - Max
1.95 V
Supply Voltage - Min
1.65 V
Maximum Operating Current
20 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
UDFN-8
12.3
Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place
the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be
ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the
mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode B9h, and
then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the CS
pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of t
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an
even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode
once the CS pin is deasserted. In addition, the device will default to the standby mode after a power cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is
in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been
completed in order for the device to enter the Deep Power-Down mode.
Figure 12-3. Deep Power-Down
SCK
CS
SO
I
CC
SI
Standby Mode Current
MSB
High-impedance
1
0
Active Current
0
1
1
2
Opcode
1
3
1
4
0
5
Deep Power-Down Mode Current
0
6
1
7
t
EDPD
AT25DL081 [DATASHEET]
8732E–DFLASH–1/2013
EDPD
.
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