AT45DB161E-SHD2B-T Adesto Technologies, AT45DB161E-SHD2B-T Datasheet - Page 8

• Manufacturer Part Number: AT45DB161E-SHD2B-T
• Description: Flash 16M 2.5-3.6V 85Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT45DB161E-SHD2B-T

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Data Flash
• Memory Size: 16 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.5 V
• Maximum Operating Current: 26 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 2000

5.3
5.4
5.5
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the f
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Continuous Array Read (High Frequency Mode: 0Bh Opcode)
This command can be used to read the main memory array sequentially at higher clock frequencies up to the maximum
specified by f
must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by three address bytes and
one dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page of the main memory
array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the starting byte address within the
page. To perform a Continuous Array Read using the binary page size (512 bytes), the opcode 0Bh must be clocked into
the device followed by three address bytes (A20 - A0) and one dummy byte. Following the dummy byte, additional clock
pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the f
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Continuous Array Read (Low Frequency Mode: 03h Opcode)
This command can be used to read the main memory array sequentially at lower clock frequencies up to maximum
specified by f
clock frequencies does not require the clocking in of dummy bytes after the address byte sequence. To perform a
Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin must first be asserted, and then
an opcode of 03h must be clocked into the device followed by three address bytes. The first 12 bits (PA11 - PA0) of the
22-bit address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 22-
bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read using the
binary page size (512 bytes), the opcode 03h must be clocked into the device followed by three address bytes (A20 -
A0). Following the address bytes, additional clock pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of
one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the f
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
Continuous Array Read (Low Power Mode: 01h Opcode)
This command is ideal for applications that want to minimize power consumption and do not need to read the memory
array at high frequencies. Like the 03h opcode, this Continuous Array Read command allows reading the main memory
array sequentially without the need for dummy bytes to be clocked in after the address byte sequence. The memory can
be read at clock frequencies up to maximum specified by f
DataFlash page size (528 bytes), the CS pin must first be asserted, and then an opcode of 01h must be clocked into the
device followed by three address bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which page
CAR1
CAR2
. To perform a Continuous Array Read using the standard DataFlash page size (528 bytes), the CS pin
. Unlike the previously described read commands, this Continuous Array Read command for the lower
CAR3
. To perform a Continuous Array Read using the standard
Adesto AT45DB161E [DATASHEET]
CAR1
CAR1
CAR2
specification. The Continuous Array
specification. The Continuous Array
specification. The Continuous Array
8782D–DFLASH–11/2012
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