AT25DL081-SSHN-B Adesto Technologies, AT25DL081-SSHN-B Datasheet - Page 11

• Manufacturer Part Number: AT25DL081-SSHN-B
• Description: Flash 8M 1.65-1.95V 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DL081-SSHN-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 8 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 1.95 V
• Supply Voltage - Min: 1.65 V
• Maximum Operating Current: 20 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8

7.2
Figure 7-4. Dual-Output Read Array
SO (SOI)
SI (SIO)
SCK
CS
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by f
perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SIO pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SIO pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SIO pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The
CS pin can be deasserted at any time and does not require that a full byte of data be read.
MSB
High-impedance
0
0
0
1
1
2
Opcode
1
3
1
4
0
5
1
6
1
7
MSB
A
8
A
9
A
Address Bits A23-A0
10 11
A
A
12
A
A
29 30
A
A
31 32
MSB
X
X
33
X
34
Don't Care
X
35
X
36
X
37 38
X
AT25DL081 [DATASHEET]
X
39
MSB
D 6
D 7
40
Data Byte 1
Output
D 4
D 5
41
D 2
D 3
42 43
D 0
D 1
8732E–DFLASH–1/2013
MSB
D 6
D 7
44
Data Byte 2
Output
D 4
D 5
45
D 2
D 3
46
D 0
D 1
47 48
MSB
D 6
D 7
RDDO
D 4
D 5
. To
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