1893BKLFT IDT, 1893BKLFT Datasheet - Page 54

• Manufacturer Part Number: 1893BKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893BKLFT

• Rohs: yes
• Part # Aliases: ICS1893BKLFT

7.2.2 Loopback Enable (bit 0.14)
7.2.3 Data Rate Select (bit 0.13)
7.2.4 Auto-Negotiation Enable (bit 0.12)
ICS1893BF, Rev. F, 5/13/10
This bit controls the Loopback mode for the ICS1893BF. Setting this bit to logic:
•
•
This bit provides a means of controlling the ICS1893BF data rate. Its operation depends on the state of
several other functions, including the HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12).
When the ICS1893BF is configured for:
•
•
This bit provides a means of controlling the ICS1893BF Auto-Negotiation sublayer. Its operation depends
on the HW/SW input pin.
When the ICS1893BF is configured for:
•
•
Zero disables the Loopback mode.
One enables the Loopback mode by disabling the Twisted-Pair Transmitter, the Twisted-Pair Receiver,
and the collision detection circuitry. (The STA can override the ICS1893BF from disabling the collision
detection circuitry in Loopback mode by writing logic one to bit 0.7.) When the ICS1893BF is in Loopback
mode, the data presented at the MAC transmit interface is internally looped back to the MAC receive
interface. The delay from the assertion of Transmit Data Enable (TXEN) to the assertion of Receive Data
valid (RXDV) is less than 512 bit times.
Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893BF isolates this bit 0.13 and uses the
10/100SEL input pin to establish the data rate for the ICS1893BF. In this Hardware mode:
Software mode (that is, the HW/SW pin is logic one), the function of bit 0.13 depends on the
Auto-Negotiation Enable bit 0.12. When the Auto-Negotiation sublayer is:
Hardware mode, (that is, the HW/SW pin is logic zero), the ICS1893BF isolates bit 0.12 and uses the
ANSEL (Auto-Negotiation Select) input pin to determine whether to enable the Auto-Negotiation
sublayer.
Note: In Hardware mode, bit 0.12 is undefined.
Software mode, (that is, the HW/SW pin is logic one), bit 0.12 determines whether to enable the
Auto-Negotiation sublayer. When bit 0.12 is logic:
– Bit 0.13 is undefined.
– The ICS1893BF provides a Data Rate Status bit (in the QuickPoll Detailed Status Register, bit 17.15),
– Enabled, the ICS1893BF isolates bit 0.13 and relies on the results of the auto-negotiation process to
– Disabled, bit 0.13 determines the data rate. In this case, setting bit 0.13 to logic:
– Zero:
– One:
ICS1893BF Data Sheet - Release
which always shows the setting of an active link.
establish the data rate.
• Zero selects 10-Mbps ICS1893BF operations.
• One selects 100-Mbps ICS1893BF operations.
• The ICS1893BF disables the Auto-Negotiation sublayer.
• The ICS1893BF bit 0.13 (the Data Rate bit) and bit 0.8 (the Duplex Mode bit) determine the data
• The ICS1893BF enables the Auto-Negotiation sublayer.
• The ICS1893BF isolates bit 0.13 and bit 0.8.
rate and the duplex mode.
Copyright © 2009, IDT, Inc.
All rights reserved.
54
Chapter 7 Management Register Set
May, 2010