1894K-40LFT IDT, 1894K-40LFT Datasheet - Page 44

• Manufacturer Part Number: 1894K-40LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-40LFT

• Rohs: yes
• Part # Aliases: ICS1894K-40LFT

100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
TP_RX
CRS
COL
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins:
•
•
•
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time
periods.
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Period
†
unscrambled.
Time
TP_RX (that is, TP_RXP and TP_RXN)
CRS
COL
Shown
†
t1
t2
t3
t4
First Bit of /J/ into TP_RX to CRS Assert †
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
First bit
Parameter
t2
t1
Half-Duplex Mode
Half-Duplex Mode
Conditions
–
–
44
First bit of /T/
t3
t4
Min. Typ. Max.
10
13
13
9
–
–
–
–
ICS1894-40
14
13
18
18
Bit times
Bit times
Bit times
Bit times
Units
PHYCEIVER
REV K 022412