1894K-40LFT IDT, 1894K-40LFT Datasheet - Page 4

• Manufacturer Part Number: 1894K-40LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-40LFT

• Rohs: yes
• Part # Aliases: ICS1894K-40LFT

IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Number
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
Notes:
1. AIO: Analog input/output PAD.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
asserted, two bits of recovered data are sent from the PHY to the MAC.
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
asserted, two bits of data are received by the PHY from the MAC.
P1/ISO/LED1
REF_OUT
P4/LED2
P0/LED0
SPEED/
REF_IN
TXCLK
Name
VDDD
TXEN
TXD0
LED3
TXD1
TXD3
TXT2
Pin
Output 25 MHz crystal output
Power
IO/Ipu
IO/Ipu
IO/Ipu
Type
Input
Input
Input
Input
Input
Input
Pin
IO
IO
10M/100M select as input (during power on reset and hardware reset)
Transmit clock as output in MII mode
Transmit enable for both RMII and MII modes
Transmit data Bit 0 for both RMII and MII modes
Core Power Supply
LED3 output
Transmit data Bit 1for both RMII and MII modes
Transmit data Bit 2 for MII mode
Transmit data Bit 3 for MII mode
25 MHz crystal (or clock) input for MII mode. 50MHz clock input for RMII mode
PHY address Bit 4 as input (always latched high during power on reset and
hardware reset) and LED # 2 as output
PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Pin Description
4
ICS1894-40
PHYCEIVER
REV K 022412