1894K-40LFT IDT, 1894K-40LFT Datasheet - Page 3

• Manufacturer Part Number: 1894K-40LFT
• Description: Ethernet ICs 3.3V 10/100 PHY RMII
• Manufacturer: IDT

Specifications of 1894K-40LFT

• Rohs: yes
• Part # Aliases: ICS1894K-40LFT

Pin Descriptions
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Number
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
AMDIX/RXD3
RMII/RXDV
RESET_N
P3/RXD2
RXCLK9
SI/LED4
HWSW/
Regpin/
ANSEL/
SPEED
TP_AN
TP_BN
RXTRI/
AMDIX
TP_AP
TP_BP
P2/INT
VDDIO
Name
FDPX/
RXER
TCSR
MDIO
RXD1
RXD0
TXER
NOD/
MDC
VDD
VDD
CRS
COL
VSS
VSS
Pin
Ground Connect to ground.
Ground Connect to ground.
Power
Power
Power
IO/Ipu
IN/Ipu
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
Type
Input
Input
Pin
AIO
AIO
AIO
AIO
AIO
Ipu
IO
IN
AMDIX Enable
Twisted pair port A (for either transmit or receive) positive signal
Twisted pair port A (for either transmit or receive) negative signal
3.3V Power Supply
Twisted pair port B (for either transmit or receive) negative signal
Twisted pair port B (for either transmit or receive) positive signal
3.3V Power Supply
Transmit Current bias pin, connected to Vdd and ground via two resistors.
Hardware reset for the whole chip (active low)
PHY address Bit 2 as input (during power on reset and hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
Management Data Input/Output
Management Data Clock
3.3 V IO Power Supply.
Hardware/Software control for phy speed as input (during power on reset and
hardware reset) and CRS output in MII mode.
Full register access enable as input (during power on reset and hardware reset) and
COL output in MII mode
AMDIX hardware enable as input (during power on reset and hardware reset)
Receive data Bit 3 as output in MII mode
PHY address Bit 3 as input (during power on reset and hardware reset)
Receive data Bit 2 as output in MII mode
RX isolate enable (during power on reset and hardware reset)
Received data Bit 1 as output in both RMII and MII modes
MII/SI mode select as input (during power on reset and hardware reset) and
LED #4 as output
Full duplex enable (during power on reset and hardware reset)
Received data Bit 0 as output in both RMII and MII modes.
RMII/MII select as input (during power on reset and hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output
10/100M input select. 1 = 100M mode, 0 = 10M mode.
TXER Input
Auto-negotiation enable(during power on reset and hardware reset)
Receive clock as output in MII mode
Node/repeater select (during power on reset and hardware reset)
Receive error as output in MII mode
Pin Description
3
ICS1894-40
PHYCEIVER
REV K 022412