100LVELT22MX Fairchild Semiconductor, 100LVELT22MX Datasheet

TRANSLATOR 3.3V DUAL DIFF 8SOIC

100LVELT22MX

Manufacturer Part Number
100LVELT22MX
Description
TRANSLATOR 3.3V DUAL DIFF 8SOIC
Manufacturer
Fairchild Semiconductor
Series
100LVELr
Datasheet

Specifications of 100LVELT22MX

Logic Function
Translator
Number Of Bits
2
Input Type
LVTTL/LVCMOS
Output Type
LVPECL
Number Of Channels
2
Number Of Outputs/channel
1
Differential - Input:output
Yes/No
Propagation Delay (max)
0.35ns
Voltage - Supply
3 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Supply Voltage
3 V ~ 3.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
© 2003 Fairchild Semiconductor Corporation
100LVELT22M
100LVELT22M8
(Preliminary)
100LVELT22
3.3V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential
LVPECL translator operating from a single 3.3V supply.
Both outputs of a differential pair should be terminated in
50
an output pair is unused both outputs can be left open
(un-terminated).
The 100 series is temperature compensated.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
to V
CC
Pin Name
Q
D
GND
- 2.0V even if only one output is being used. If
V
n
0
, Q
, D
CC
n
1
Package
Number Top Mark
MA08D
M08A
Top View
LVPECL Differential Outputs
LVTTL/LVCMOS Inputs
Positive Supply
Ground
Product
KVT22
Code
KR22
Description
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
DS500777
Features
Logic Diagram
Typical propagation delay of 350 ps
Max I
When TTL input is left Open Q output defaults HIGH
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
Flow through pinout
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
Moisture Sensitivity Level 1
ESD Performance:
Human Body Model
Machine Model
100 ps skew between outputs
CC
Package Description
of 28 mA at 25 C
200V
2000V
January 2003
Revised January 2003
www.fairchildsemi.com

Related parts for 100LVELT22MX

100LVELT22MX Summary of contents

Page 1

... LVTTL/LVCMOS Inputs Positive Supply CC GND Ground © 2003 Fairchild Semiconductor Corporation Features Typical propagation delay of 350 ps 100 ps skew between outputs Max When TTL input is left Open Q output defaults HIGH Fairchild MSOP-8 package is a drop-in replacement to ON TSSOP-8 Flow through pinout Meets or exceeds JEDEC specification EIA/JESD78 IC ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Current (I ) OUT Continuous Surge Storage Temperature (T ) STG LVPECL DC Electrical Characteristics Symbol Parameter I Power Supply Current ...

Page 3

Switching Waveforms FIGURE 1. LVTTL to Differential LVPECL Propagation Delay FIGURE 2. Differential Output Edge Rates 3 www.fairchildsemi.com ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M08A 4 ...

Page 5

Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit ...

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