LFE3-95EA-7LFN484C Lattice, LFE3-95EA-7LFN484C Datasheet - Page 46

• Manufacturer Part Number: LFE3-95EA-7LFN484C
• Description: FPGA - Field Programmable Gate Array 92K LUTs 133 I/O 1.2V -7 SPEED
• Manufacturer: Lattice

Specifications of LFE3-95EA-7LFN484C

• Rohs: yes
• Number Of Gates: 92 K
• Number Of Logic Blocks: 240
• Embedded Block Ram - Ebr: 4420 Kbit
• Number Of I/os: 133
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-484
• Distributed Ram: 188 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 137.3 mA
• Factory Pack Quantity: 60

On-Chip Programmable Termination
The LatticeECP3 supports a variety of programmable on-chip terminations options, including:
Figure 2-39. On-Chip Termination
See Table 2-12 for termination options for input modes.
Table 2-12. On-Chip Termination Options for Input Modes
• Dynamically switchable Single-Ended Termination with programmable resistor values of 40, 50, or 60 ohms.
• Common mode termination of 80, 100, 120 ohms for differential inputs
External termination to Vtt should be used for DDR2 and DDR3 memory controller implementation.
LVDS25
BLVDS25
MLVDS
HSTL18_I
HSTL18_II
HSTL18D_I
HSTL18D_II
HSTL15_I
HSTL15D_I
SSTL25_I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL18_II
SSTL18D_I
SSTL18D_II
SSTL15
SSTL15D
1. TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR when turned on can only have
2. External termination to VTT should be used when implementing DDR2 and DDR3 memory controller.
one setting per bank. Only left and right banks have this feature.
Use of TERMINATE to VTT and DIFFRENTIAL TERMINATION RESISTOR are mutually exclusive in
an I/O bank.
On-chip termination tolerance +/- 20%
Programmable resistance (40, 50 and 60 Ohms)
IO_TYPE
Parallel Single-Ended Input
Off-chip
Vtt
TERMINATE to VTT
On-Chip
Zo
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
40, 50, 60
þ
þ
þ
+
Control Signal
-
1, 2
2-43
DIFFERENTIAL TERMINATION RESISTOR
Off-chip
*Vtt must be left floating for this termination
On-Chip
80, 100, 120
80, 100, 120
80, 100, 120
Vtt*
Differential Input
LatticeECP3 Family Data Sheet
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
þ
Z0
Z0
+
-
1
Architecture