LFE3-95EA-7LFN484C Lattice, LFE3-95EA-7LFN484C Datasheet - Page 29

• Manufacturer Part Number: LFE3-95EA-7LFN484C
• Description: FPGA - Field Programmable Gate Array 92K LUTs 133 I/O 1.2V -7 SPEED
• Manufacturer: Lattice

Specifications of LFE3-95EA-7LFN484C

• Rohs: yes
• Number Of Gates: 92 K
• Number Of Logic Blocks: 240
• Embedded Block Ram - Ebr: 4420 Kbit
• Number Of I/os: 133
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-484
• Distributed Ram: 188 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 137.3 mA
• Factory Pack Quantity: 60

MMAC DSP Element
The LatticeECP3 supports a MAC with two multipliers. This is called Multiply Multiply Accumulate or MMAC. In this
case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated value and
with the result of the multiplier operation of operands BA and BB. This accumulated value is available at the output.
The user can enable the input and pipeline registers, but the output register is always enabled. The output register
is used to store the accumulated value. The ALU is configured as the accumulator in the sysDSP slice. A registered
overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-28 shows the
MMAC sysDSP element.
Figure 2-28. MMAC sysDSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
IR
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-26
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
OR
PR
IR
BB
IR
COUT
SROB
SROA
DSP Slice
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Architecture