LFE3-95EA-7LFN484C Lattice, LFE3-95EA-7LFN484C Datasheet - Page 38

• Manufacturer Part Number: LFE3-95EA-7LFN484C
• Description: FPGA - Field Programmable Gate Array 92K LUTs 133 I/O 1.2V -7 SPEED
• Manufacturer: Lattice

Specifications of LFE3-95EA-7LFN484C

• Rohs: yes
• Number Of Gates: 92 K
• Number Of Logic Blocks: 240
• Embedded Block Ram - Ebr: 4420 Kbit
• Number Of I/os: 133
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-484
• Distributed Ram: 188 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 137.3 mA
• Factory Pack Quantity: 60

Figure 2-34. Output and Tristate Block for Left and Right Edges
Tristate Register Block
The tristate register block registers tri-state control signals from the core of the device before they are passed to the
sysI/O buffers. The block contains a register for SDR operation and an additional register for DDR operation.
In SDR and non-gearing DDR modes, TS input feeds one of the flip-flops that then feeds the output. In DDRX2
mode, the register TS input is fed into another register that is clocked using the DQCLK0 and DQCLK1 signals. The
output of this register is used as a tristate control.
ISI Calibration
The setting for Inter-Symbol Interference (ISI) cancellation occurs in the output register block. ISI correction is only
available in the DDRX2 modes. ISI calibration settings exist once per output register block, so each I/O in a DQS-
12 group may have a different ISI calibration setting.
The ISI block extends output signals at certain times, as a function of recent signal history. So, if the output pattern
consists of a long strings of 0's to long strings of 1's, there are no delays on output signals. However, if there are
quick, successive transitions from 010, the block will stretch out the binary 1. This is because the long trail of 0's will
cause these symbols to interfere with the logic 1. Likewise, if there are quick, successive transitions from 101, the
block will stretch out the binary 0. This block is controlled by a 3-bit delay control that can be set in the DQS control
logic block.
For more information about this topic, please see the list of technical documentation at the end of this data sheet.
DQCLK1
DQCLK0
ONEGA
ONEGB
OPOSA
OPOSB
SCLK
TS
Clock
Transfer
Registers
Config Bit
D Q
CE
D Q
CE
D Q
D Q
D Q
R
R
D1
C1
D Q
D Q
L
L
D Q
2-35
C
D
A
B
11
10
00
01
DDR Gearing &
ISI Correction
LatticeECP3 Family Data Sheet
ISI
Tristate Logic
Output Logic
Architecture
TO
DO