M95M01-DFDW6TP STMicroelectronics, M95M01-DFDW6TP Datasheet - Page 17
M95M01-DFDW6TP
Manufacturer Part Number
M95M01-DFDW6TP
Description
EEPROM 1Mb SPI bus EEPROM 256kB 16MHz
Manufacturer
STMicroelectronics
Datasheet
1.M95M01-DFDW6TP.pdf
(45 pages)
Specifications of M95M01-DFDW6TP
Rohs
yes
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M95M01-DF M95M01-R
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.
Figure 8.
Figure
Write Enable (WREN) sequence
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 13264 Rev 11
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI02281E
Instructions
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