CAV25640VE-GT3 ON Semiconductor, CAV25640VE-GT3 Datasheet - Page 10

• Manufacturer Part Number: CAV25640VE-GT3
• Description: EEPROM 64KB SPI SER CMOS EEPROM
• Manufacturer: ON Semiconductor

Specifications of CAV25640VE-GT3

• Product Category: EEPROM

Hold Operation
between host and CAV25640. To pause, HOLD must be
taken low while SCK is low (Figure 11). During the hold
condition the device must remain selected (CS low). During
the pause, the data output pin (SO) is tri−stated (high
impedance) and SI transitions are ignored. To resume
communication, HOLD must be taken high while SCK is low.
Design Considerations
(POR) circuitry which protects the internal logic against
powering up in the wrong state. The device will power up
into Standby mode after V
and will power down into Reset mode when V
The HOLD input can be used to pause communication
The CAV25640 device incorporates Power−On Reset
HOLD
SCK
CS
SO
Dashed Line = mode (1, 1)
CC
exceeds the POR trigger level
t
HD
t
CD
t
HZ
Figure 11. HOLD Timing
CC
http://onsemi.com
drops
10
HIGH IMPEDANCE
below the POR trigger level. This bi−directional POR
behavior protects the device against ‘brown−out’ failure
following a temporary loss of power.
and in a low power standby mode. A WREN instruction
must be issued prior to any writes to the device.
a ready state and receive an instruction. After a successful
byte/page write or status register write, the device goes into
a write disable mode. The CS input must be set high after the
proper number of clock cycles to start the internal write
cycle. Access to the memory array during an internal write
cycle is ignored and programming is continued. Any invalid
op−code will be ignored and the serial output pin (SO) will
remain in the high impedance state.
The CAV25640 device powers up in a write disable state
After power up, the CS pin must be brought low to enter
t
HD
t
CD
t
LZ