CAV25640VE-GT3 ON Semiconductor, CAV25640VE-GT3 Datasheet
CAV25640VE-GT3
Specifications of CAV25640VE-GT3
Related parts for CAV25640VE-GT3
CAV25640VE-GT3 Summary of contents
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... SPI Serial CMOS EEPROM Description The CAV25640 is a 64−Kb Serial CMOS EEPROM device internally organized as 8Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines ...
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AYMXXX G (SOIC−8) 25640F = Specific Device Code A = Assembly Location Y = Production Year (Last Digit Production Month (1− XXX = Last Three Digits of XXX = Assembly Lot Number G = ...
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Table 4. PIN CAPACITANCE (T = 25° 1.0 MHz Symbol Test C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI, WP, HOLD) IN Table 5. A.C. CHARACTERISTICS Symbol f Clock Frequency SCK t Data ...
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Pin Description SI: The serial data input pin accepts op−codes, addresses and data. In SPI modes (0,0) and (1,1) input data is latched on the rising edge of the SCK clock input. SO: The serial data output pin is used ...
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Status Register The Status Register, as shown in Table 8, contains a number of status and control bits. The RDY (Ready) bit indicates whether the device is busy with a write operation. This bit is automatically set to 1 during ...
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The CAV25640 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In addition, the address of ...
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Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 13 significant address bits are used by the CAV25640. ...
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Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 7. Only bits 2, 3 and 7 can be written using the WRSR command SCK OPCODE ...
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Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16−bit address (see Table 11 for the number of significant address bits). After receiving the last address bit, the CAV25640 will respond by ...
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Hold Operation The HOLD input can be used to pause communication between host and CAV25640. To pause, HOLD must be taken low while SCK is low (Figure 11). During the hold condition the device must remain selected (CS low). During ...
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PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...
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E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...
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D E PIN#1 INDEX AREA TOP VIEW SYMBOL MIN NOM A 0.70 0.75 A1 0.00 0.02 A2 0.45 0.55 A3 0.20 REF b 0.20 0.25 D 1.90 2.00 D2 1.30 1.40 E 2.90 3.00 E2 1.20 1.30 e 0.50 TYP ...
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... ORDERING INFORMATION (Notes 8 − 10) Device Order Number Specific Device Marking CAV25640VE−GT3 CAV25640YE−GT3 CAV25640VP2E−GT3 8. All packages are RoHS−compliant (Lead−free, Halogen−free). 9. The standard lead finish is NiPdAu. 10. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. ...