KPC8544EVTANG Freescale Semiconductor, KPC8544EVTANG Datasheet - Page 108

• Manufacturer Part Number: KPC8544EVTANG
• Description: Microprocessors - MPU PQ38K 8544E
• Manufacturer: Freescale Semiconductor

Specifications of KPC8544EVTANG

• Product Category: Microprocessors - MPU
• Rohs: yes
• Maximum Clock Frequency: 800 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: FCPBGA
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Factory Pack Quantity: 5

System Design Information
21.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to V
required. All unused active high inputs should be connected to GND. All NC (no connect) signals must
remain unconnected. Power and ground connections must be made to all external V
OV
21.6
The MPC8544E requires weak pull-up resistors (2–10 kΩ is recommended) on open drain type pins
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must NOT be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1] and TEST_SEL pins
must be set to a proper state during POR configuration. Refer to the pinout listing table
details. Refer to the PCI 2.2 Local Bus Specifications, for all pullups required for PCI.
21.7
The MPC8544E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
external resistor is connected from the chip pad to OV
until the pad voltage is OV
the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open)
108
DD
, GV
Connection Recommendations
Pull-Up and Pull-Down Resistor Requirements
Output Buffer DC Impedance
2
DD
C pins and MPIC interrupt pins.
, and LV
Figure
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
DD
69. Care must be taken to ensure that these pins are maintained at a valid deasserted
, and GND pins of the device.
DD
/2 (see
Figure
67). The output impedance is the average of two components,
DD
DD
2
C). To measure Z
or GND. Then, the value of each resistor is varied
, TV
DD
, BV
DD
, OV
0
for the single-ended drivers, an
DD
, GV
DD
Freescale Semiconductor
DD
(Table
, TV
, and LV
DD
62) for more
, BV
DD
DD
as
,