STM32F207ICH6 STMicroelectronics, STM32F207ICH6 Datasheet - Page 171

• Manufacturer Part Number: STM32F207ICH6
• Description: ARM Microcontrollers - MCU 32-Bit ARM Cortex M3 CAM 256 kB
• Manufacturer: STMicroelectronics

Specifications of STM32F207ICH6

• Product Category: ARM Microcontrollers - MCU
• Rohs: yes
• Core: ARM Cortex M3
• Data Bus Width: 32 bit

STM32F20xxx
Table 94.
22-Apr-2011
Date
Document revision history (continued)
(continued)
Revision
6
Changed t
t
bus AC waveforms and measurement
Added
updated
Updated V
characteristics.
Updated
Updated R
Updated t
Updated R typical value in
Updated
Modified FSMC_NOE waveform in
multiplexed SRAM/PSRAM/NOR read
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed t
AIV)
NWEH)
Synchronous multiplexed NOR/PSRAM read
Synchronous multiplexed PSRAM write
Synchronous non-multiplexed NOR/PSRAM read
Figure 61: Synchronous non-multiplexed PSRAM write
Changed t
t
modified t
Table
Updated note 2 in
Table
Modified t
waveforms for I/O space write
Modified FSMC_NCEx signal in
waveforms for read
write
memory read
common memory write access
Specified Full speed (FS) mode for
peripheral-only connection in FS mode
host-only connection in FS
f(SCK)
d(CLKH-NOEH)
, t
Doc ID 15818 Rev 9
d(CLKH-NOEH)
access,
77.
75,
, and updated data latency from 1 to 0 in
to t
Table 55: USB OTG FS DC electrical characteristics
Table 56: USB OTG FS electrical
Table 64: ADC characteristics
Table 69: Embedded internal reference
Table
f(SCL)
START
w(CLK)
h(NIOWR-D)
w(SCKH)
d(CLKH-NExH
DD
AIN
Figure 70: NAND controller waveforms for common
minimum value in
access, and
to t
equation. Updated
in
76, and
in
minimum value in
d(CLKL-NOEH)
d(CLKH-NExH
Table 50: I2C characteristics
Table 67: TS
to t
Table
to t
access,
in
w(SCLH)
d(CLKL-NOEH)
) to t
Figure 67: PC Card/CompactFlash controller
Table
70,
d(CLKL-NExH)
Figure 71: NAND controller waveforms for
Table 68: VBAT monitoring
mode.
Figure 69: NAND controller waveforms for
Table
, t
) to t
, t
77.
Changes
access.
w(SCKL)
characteristics.
d(CLKH-NWEH)
Table 60: Ethernet DC electrical
Figure 68: NAND controller
Table 66: DAC
d(CLKL-NExH)
71,
Table
, and t
Figure 54: Asynchronous non-
Figure 89: USB OTG HS
Table
circuit.
to t
waveforms. Shifted end of
, t
and R
and
timings,
74,
d(CLKH-AIV)
d(CLKH-NWEH)
w(SCLL)
characteristics.
Figure 90: USB OTG HS
72,
Table
timings,
AIN
to t
, t
and in
Figure 58:
d(CLKH-AIV)
Table
Figure 60:
characteristics.
, t
d(CLKL-NWEH)
voltage.
equation.
timings, and
75,
r(SCK)
to t
Revision history
Figure 59:
73,
Figure 38: I2C
Table
characteristics.
to t
d(CLKL-AIV)
timings,
to t
Table
d(CLKL-
to t
r(SCL)
and
76, and
, and
d(CLKL-
171/177
74,
, and
,