MPC8308CVMAGDA Freescale Semiconductor, MPC8308CVMAGDA Datasheet - Page 54
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MPC8308CVMAGDA
Manufacturer Part Number
MPC8308CVMAGDA
Description
Microprocessors - MPU E300 EXT TMP 400
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8308VMAGDA.pdf
(83 pages)
Specifications of MPC8308CVMAGDA
Rohs
yes
Processor Series
MPC8308
Core
e300
Maximum Clock Frequency
400 MHz
Interface Type
I2C, JTAG, UART
Operating Supply Voltage
0.95 V to 1.05 V
Maximum Operating Temperature
- 40 C to + 105 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-473
Available stocks
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Manufacturer
Quantity
Price
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All values refer to V
I
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including hysteresis)
Noise margin at the HIGH level for each connected device (including hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
5. The device does not follow the I
This figure provides the AC test load for the I
This figure shows the AC timing diagram for the I
54
2
C
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
went invalid (X) relative to the t
(I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
(K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
undefined region of the falling edge of SCL.
B
SDA
= capacitance of one bus line in pF.
SCL
(first two letters of functional block)(reference)(state)(signal)(state)
S
IH
I2DXKL
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the LOW period (t
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Output
IL
(max) levels (see
Table 44. I
I2SXKL
I2C
2
C-BUS Specifications, Version 2.1, regarding the t
clock reference (K) going to the low (L) state or hold time. Also, t
Parameter
symbolizes I
Figure 46. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Table
Figure 45. I
Z
t
I2DVKH
0
2
= 50
C timing (I2) for the time that the data with respect to the start condition (S)
43).
t
I2CH
2
2
C Bus AC Timing Diagram
C.
t
I2SXKL
2
2
C AC Test Load
C bus.
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. For example, t
Sr
t
I2SVKH
t
I2KHKL
R
L
= 50
I2CF
I2C
IHmin
t
AC parameter.
I2PVKH
Symbol
clock reference (K) going to the high
t
t
I2PVKH
I2CL
NV
I2KHDX
V
V
I2DVKH
of the SCL signal) to bridge the
NH
NL
DD
t
) of the SCL signal.
I2CR
/2
I2PVKH
1
symbolizes I
Freescale Semiconductor
0.1 NV
0.2 NV
P
symbolizes I
Min
0.6
1.3
t
I2CF
I2C
DD
DD
clock reference
2
C timing (I2)
S
Max Unit
—
—
—
—
2
C timing
for
s
s
V
V