MK12DN512VLK5 Freescale Semiconductor, MK12DN512VLK5 Datasheet - Page 46

• Manufacturer Part Number: MK12DN512VLK5
• Description: ARM Microcontrollers - MCU ARM+512Kb
• Manufacturer: Freescale Semiconductor

Specifications of MK12DN512VLK5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK12DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Power modes
1. Resumes normal run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.
46
VLPS (Very Low
Power Stop)-via
Leakage Stop)
Low Leakage
Low Leakage
Low Leakage
Low Leakage
BAT (backup
VLLS3 (Very
VLLS2 (Very
VLLS1 (Very
VLLS0 (Very
battery only)
Chip mode
LLS (Low
Stop 0)
Stop3)
Stop2)
Stop1)
WFI
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional. Peripheral clocks are stopped,
but LPTimer, RTC, CMP, DAC can be used. NVIC is disabled (FCLK =
OFF); AWIC is used to wake up from interrupt. On-chip voltage
regulator is in a low power mode that supplies only enough power to
run the chip at a reduced frequency. All SRAM is operating (content
retained and I/O states held).
State retention power mode. Most peripherals are in state retention
mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, DAC can
be used. NVIC is disabled; LLWU is used to wake up.
NOTE: The LLWU interrupt must not be masked by the interrupt
All SRAM is operating (content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_U and SRAM_L remain powered on (content retained and I/O
states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
SRAM_L is powered off. A portion of SRAM_U remains powered on
(content retained and I/O states held).
Most peripherals are disabled (with clocks stopped), but LLWU,
LPTimer, RTC, CMP, DAC can be used. NVIC is disabled; LLWU is
used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
Most peripherals are disabled (with clocks stopped), but LLWU and
RTC can be used. NVIC is disabled; LLWU is used to wake up.
All of SRAM_U and SRAM_L are powered off. The 32-byte system
register file and the 32-byte VBAT register file remain powered for
customer-critical data.
The POR detect circuit can be optionally powered off.
The chip is powered down except for the VBAT supply. The RTC and
the 32-byte VBAT register file for customer-critical data remain
powered.
Description
controller to avoid a scenario where the system does not fully
exit stop mode on an LLS recovery.
Table 10. Chip power modes (continued)
K10 Family Product Brief, Rev. 11, 08/2012
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Sleep Deep
Core mode
Freescale Semiconductor, Inc.
Off
Wakeup Reset
Wakeup Reset
Wakeup Reset
Wakeup Reset
Sequence
Power-up
Interrupt
recovery
Interrupt
Wakeup
method
Normal
1
2
2
2
2