MK12DN512VLK5 Freescale Semiconductor, MK12DN512VLK5 Datasheet - Page 43

• Manufacturer Part Number: MK12DN512VLK5
• Description: ARM Microcontrollers - MCU ARM+512Kb
• Manufacturer: Freescale Semiconductor

Specifications of MK12DN512VLK5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK12DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

4.5.7.2 Serial Peripheral Interface (SPI)
4.5.7.3 Inter-Integrated Circuit (I
4.5.7.4 UART
Freescale Semiconductor, Inc.
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8-bit or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed transfers of large amounts of data
• Support for both transmit and receive by DMA
• Compatible with I
• Up to 100 kbps with maximum bus loading
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt or DMA driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low power mode
• Support for ISO 7816 protocol for interfacing with smartcards
• Full-duplex operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Parameterizable buffer support for one dataword for each transmit and receive
• Independent FIFO structure for transmit and receive
• Two receiver wakeup methods:
• Address match feature in receiver to reduce address mark wakeup ISR overhead
• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
• Support for CEA709.1-B protocol (LON) used in building automation and home networking systems
• Interrupt or DMA driven operation
• Receiver framing error detection
• Idle line wakeup
• Address mark wakeup
2
C bus standard and SMBus Specification Version 2 features
K10 Family Product Brief, Rev. 11, 08/2012
2
C)
Communication interfaces
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