MK12DN512VLK5 Freescale Semiconductor, MK12DN512VLK5 Datasheet - Page 45

• Manufacturer Part Number: MK12DN512VLK5
• Description: ARM Microcontrollers - MCU ARM+512Kb
• Manufacturer: Freescale Semiconductor

Specifications of MK12DN512VLK5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK12DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

4.5.8.2 Touch Sensor Input (TSI)
5 Power modes
The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption
for the level of functionality needed.
Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention,
partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The
following table compares the various power modes available.
For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes
(VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce
runtime power when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the
chip. The primary modes are augmented in a number of ways to provide lower power based on application needs.
Freescale Semiconductor, Inc.
VLPR (Very Low
Wait) -via WFI
Normal Stop -
Normal Wait -
VLPW (Very
Power Run)
Chip mode
Normal run
Low Power
• Configurable slew rate and drive strength on all output pins
• Independent pin value register to read logic level on digital pin
• Optional devices with 5V tolerance
• 16 channel inputs, supporting up to 16 individual touch buttons
• 4 touch buttons can be combined for a slider
• Configurable button- and slider-sensitive interrupts
• Operation in low-power modes allows wakeup from lowest power mode via a single touch
• Option to use internal reference clock
via WFI
via WFI
Allows maximum performance of chip. Default mode out of reset; on-
chip voltage regulator is on.
Allows peripherals to function while the core is in sleep mode, reducing
power. NVIC remains sensitive to interrupts; peripherals continue to be
clocked.
Places chip in static state. Lowest power mode that retains all registers
while maintaining LVD protection. NVIC is disabled; AWIC is used to
wake up from interrupt; peripheral clocks are stopped.
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency. Reduced
frequency Flash access mode (1 MHz); LVD off; internal oscillator
provides a low power 4 MHz source for the core, the bus and the
peripheral clocks.
Same as VLPR but with the core in sleep mode to further reduce
power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip
voltage regulator is in a low power mode that supplies only enough
power to run the chip at a reduced frequency.
Description
K10 Family Product Brief, Rev. 11, 08/2012
Table 10. Chip power modes
Table continues on the next page...
Sleep Deep
Core mode
Sleep
Sleep
Run
Run
Power modes
recovery
Interrupt
Interrupt
Interrupt
Interrupt
method
Normal
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