MK12DN512VLK5 Freescale Semiconductor, MK12DN512VLK5 Datasheet - Page 42

• Manufacturer Part Number: MK12DN512VLK5
• Description: ARM Microcontrollers - MCU ARM+512Kb
• Manufacturer: Freescale Semiconductor

Specifications of MK12DN512VLK5

• Rohs: yes
• Core: ARM Cortex M4
• Processor Series: MK12DN512
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Communication interfaces
4.5.6.5 Carrier Modulator Timer (CMT)
4.5.6.6 Real-Time Clock (RTC)
4.5.7
4.5.7.1 CAN Module
42
• Selectable clock for prescaler/glitch filter
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Four modes of operation
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
• Independent power supply, POR and 32 kHz crystal oscillator
• 32-bit seconds counter with 32-bit alarm
• 16-bit prescaler with compensation
• Register write protection
• Supports the full implementation of the CAN Specification Version 2.0, Part B
• Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 bytes data length each, configurable as Rx
• Listen-only mode capability
• Individual mask registers for each message buffer
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Timestamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
or Tx, all supporting standard and extended messages
• 1 kHz internal LPO
• External low power crystal oscillator
• Internal reference clock (not available in low leakage power modes)
• Secondary external reference clock (for example, 32 kHz crystal)
• Time with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Hard Lock requires VBAT POR to enable write access
• Soft lock requires system reset to enable write/read access
• Standard data and remote frames (up to 109 bits long)
• Extended data and remote frames (up to 127 bits long)
• 0–8 bytes data length
• Programmable bit rate up to 1 Mbit/sec
• Content-related addressing
Communication interfaces
K10 Family Product Brief, Rev. 11, 08/2012
Freescale Semiconductor, Inc.