W65C816S6PG-14 Western Design Center (WDC), W65C816S6PG-14 Datasheet - Page 19

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W65C816S6PG-14

Manufacturer Part Number
W65C816S6PG-14
Description
Microprocessors - MPU 8/16-bit Microprocessor
Manufacturer
Western Design Center (WDC)
Datasheet

Specifications of W65C816S6PG-14

Rohs
yes
Processor Series
65x
Data Bus Width
8 bit, 16 bit
Maximum Clock Frequency
14 MHz
Operating Supply Voltage
1.8 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-40
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
10
3.5.1 Absolute-a
With Absolute addressing the second and third bytes of the instruction form the low order 16 bits of the
effective address. The Data Bank Register contains the high order 8 bits of the operand address.
3.5.2 Absolute Indexed Indirect-(a,x)
With Absolute Indexed Indirect ((a,x)) addressing the second and third bytes of the instruction are
added to the X Index Register to form a 16-bit pointer in Bank 0. The contents of this pointer are loaded
in the Program Counter for the JMP instruction. The Program Bank Register is not changed.
then:
PC = (address)
3.5.3 Absolute Indexed with X-a,x
With Absolute Indexed with X (a,x) addressing the second and third bytes of the instruction are added
to the X Index Register to form the low order 16 bits of the effective address. The Data Bank Register
contains the high order 8 bits of the effective address.
3.5.4 Absolute Indexed with Y-a,y
With Absolute Indexed with Y (a,y) addressing the second and third bytes of the instruction are added
to the Y Index Register to form the low order 16 bits of the effective address. The Data Bank Register
contains the high order 8 bits of the effective address.
Instruction:
Instruction:
Operand
Address:
Instruction:
Operand
Address:
Opcode
Opcode
Opcode
PBR
DBR
DBR
effective address
effective address
+
+
addrh
addrl
addrh
addrl
addrh
addrl
address
X Reg
X Reg
addrh
addrh
Y Reg
addrl
addrl
addrh
addrl
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