W65C816S6PG-14 Western Design Center (WDC), W65C816S6PG-14 Datasheet - Page 15

• Manufacturer Part Number: W65C816S6PG-14
• Description: Microprocessors - MPU 8/16-bit Microprocessor
• Manufacturer: Western Design Center (WDC)

Specifications of W65C816S6PG-14

• Rohs: yes
• Processor Series: 65x
• Data Bus Width: 8 bit, 16 bit
• Maximum Clock Frequency: 14 MHz
• Operating Supply Voltage: 1.8 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 10

2.16 Data/Bank Address Bus (D0-D7)
The Data/Bank Address Bus pins provide both the Bank Address and Data. The bank address is present
during the first half of a memory cycle, and the data value is read or written during the second half of the
memory cycle. Two memory cycles are required to transfer 16-bit values. These lines may be set to the
high impedance state by the Bus Enable (BE) signal.
2.17 Emulation Status (E)
The Emulation Status output reflects the state of the Emulation (E) mode flag in the Processor Status (P)
Register. This signal may be thought of as an opcode extension and used for memory and system
management.
2.18 Interrupt Request (IRQB)
The Interrupt Request negative level active input signal is used to request that an interrupt sequence be
initiated. When the IRQB Disable flag is cleared, a low input logic level initiates an interrupt sequence after
the current instruction is completed. The Wait for Interrupt (WAI) instruction may be executed to ensure the
interrupt will be recognized immediately. The Interrupt Request vector address is 00FFFE, F (Emulation
mode) or 00FFEE,F (Native mode). Since IRQB is a level sensitive input, an interrupt will occur if the
interrupt source was not cleared since the last interrupt. Also, no interrupt will occur if the interrupt source is
cleared prior to interrupt recognition. The IRQB signal going low causes 4 bytes of information to be pushed
onto the stack before jumping to the interrupt handler. The first byte is PBR followed by PCH, PCL and P
(Processor Status Register). These register values are used by the RTI instruction to return the processor
to its original state prior to handling the IRQ interrupt (see Table 6-1)
2.19 Memory Lock (MLB)
The Memory Lock active low output may be used to ensure the integrity of Read Modify Write instructions in
a multiprocessor system. Memory Lock indicates the need to defer arbitration of the next bus cycle.
Memory Lock is low during the last three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB
memory referencing instructions, depending on the state of the M flag.
2.20 Memory/Index Select Status (MX)
The Memory/Index Select Status multiplexed output reflects the state of the Accumulator (M) and Index (X)
elect flags (bits 5 and 4 of the Processor Status (P) Register. Flag M is valid during PHI2 negative transition
and Flag X is valid during PHI2 positive transition. These bits may be thought of as opcode extensions and
may be used for memory and system management.
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