LPC1778FBD144,551 NXP Semiconductors, LPC1778FBD144,551 Datasheet - Page 89

• Manufacturer Part Number: LPC1778FBD144,551
• Description: ARM Microcontrollers - MCU CORTEX-M3 512KB FL 96KB SRAM USB 2.0
• Manufacturer: NXP Semiconductors

Specifications of LPC1778FBD144,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC178x
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 120 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 8
• Interface Type: CAN, I2C, I2S, SSP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 165
• Number Of Timers: 4
• On-chip Dac: Yes
• Program Memory Type: Flash
• Factory Pack Quantity: 60
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.4 V

NXP Semiconductors
LPC178X_7X
Product data sheet
Table 24.
C
[1]
[2]
[3]
[4]
Symbol
SSP slave
T
t
T
t
t
t
DS
DH
v(Q)
h(Q)
Fig 21. SSP master timing in SPI mode
L
cy(PCLK)
cy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
= 10 pF, T
T
T
SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in
the SSP clock prescale register).
T
T
T
cy(clk)
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C; V
= 25 C; V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
is a function of the main clock frequency f
= 12  T
MOSI
MISO
MOSI
MISO
Dynamic characteristics: SSP pins in SPI mode
amb
Parameter
PCLK cycle time
clock cycle time
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
=
All information provided in this document is subject to legal disclaimers.
cy(PCLK)
DD(3V3)

40
Rev. 4.1 — 15 November 2012

C to 85
.
= 3.3 V.
DATA VALID
DATA VALID
DD(3V3)
t
v(Q)

C, V
= 3.0 V to 3.6 V.
DATA VALID
T
DATA VALID
Conditions
in SPI mode
in SPI mode
DD(3V3)
cy(clk)
t
v(Q)
t
DS
= 3.0 V to 3.6 V. Values guaranteed by design.
DATA VALID
DATA VALID
main
main
, the SSP peripheral clock divider (SSPCLKDIV), the
t
clk(H)
t
. 4The clock cycle time derived from the SPI bit rate
t
DH
DS
32-bit ARM Cortex-M3 microcontroller
[3]
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
DATA VALID
Min
10
120
14.8
2
-
2.4
t
clk(L)
t
DH
t
h(Q)
LPC178x/7x
Max
-
-
-
6.3
-
t
h(Q)
© NXP B.V. 2012. All rights reserved.
CPHA = 1
CPHA = 0
Unit
ns
ns
ns
ns
ns
ns
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